Datasheet
PIC17C7XX
DS30289C-page 114 1998-2013 Microchip Technology Inc.
13.2.4 EXTERNAL CLOCK INPUT FOR
TIMER3
When TMR3CS is set, the 16-bit TMR3 increments on
the falling edge of clock input TCLK3. The input on the
RB5/TCLK3 pin is sampled and synchronized by the
internal phase clocks, twice every instruction cycle.
This causes a delay from the time a falling edge
appears on TCLK3 to the time TMR3 is actually incre-
mented. For the external clock input timing require-
ments, see the Electrical Specification section.
Figure 13-7 shows the timing diagram when operating
from an external clock.
13.2.5 READING/WRITING TIMER3
Since Timer3 is a 16-bit timer and only 8-bits at a time
can be read or written, care should be taken when
reading or writing while the timer is running. The best
method is to stop the timer, perform any read or write
operation and then restart Timer3 (using the TMR3ON
bit). However, if it is necessary to keep Timer3 free-
running, care must be taken. For writing to the 16-bit
TMR3, Example 13-2 may be used. For reading the 16-
bit TMR3, Example 13-3 may be used. Interrupts must
be disabled during this routine.
EXAMPLE 13-2: WRITING TO TMR3
EXAMPLE 13-3: READING FROM TMR3
FIGURE 13-7: TIMER1, TIMER2 AND TIMER3 OPERATION (IN COUNTER MODE)
BSF CPUSTA, GLINTD ; Disable interrupts
MOVFP RAM_L, TMR3L ;
MOVFP RAM_H, TMR3H ;
BCF CPUSTA, GLINTD ; Done, enable interrupts
MOVPF TMR3L, TMPLO ; read low TMR3
MOVPF TMR3H, TMPHI ; read high TMR3
MOVFP TMPLO, WREG ; tmplo wreg
CPFSLT TMR3L ; TMR3L < wreg?
RETURN ; no then return
MOVPF TMR3L, TMPLO ; read low TMR3
MOVPF TMR3H, TMPHI ; read high TMR3
RETURN ; return
Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4
Instruction
Executed
MOVWF MOVFP
TMRx,WTMRx
MOVFP
TMRx,W
Write to TMRx Read TMRx Read TMRx
34h 35h A8h A9h 00h
'A9h' 'A9h'
TCLK12
TMR1, TMR2, or TMR3
PR1, PR2, or PR3H:PR3L
WR_TMR
RD_TMR
TMRxIF
Note 1: TCLK12 is sampled in Q2 and Q4.
2: indicates a sampling point.
3: The latency from TCLK12 to timer increment is between 2Tosc and 6Tosc.
or TCLK3