Datasheet

PIC17C4X
DS30412C-page 92  1996 Microchip Technology Inc.
Steps to follow when setting up an Asynchronous
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. Enable the reception by setting the CREN bit.
6. The RCIF bit will be set when reception com-
pletes and an interrupt will be generated if the
RCIE bit was set.
7. Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
8. Read RCREG for the 8-bit received data.
9. If an overrun error occurred, clear the error by
clearing the OERR bit.
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
FIGURE 13-8: ASYNCHRONOUS RECEPTION
TABLE 13-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-on
Reset
Value on all
other resets
(Note1)
16h, Bank 1 PIR
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010
13h, Bank 0 RCSTA SPEN RX9 SREN CREN
— FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 0 RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
17h, Bank 1 PIE
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TXIE RCIE 0000 0000 0000 0000
15h, Bank 0 TXSTA
CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG Baud rate generator register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
Start
bit
bit7/8
bit1bit0
bit7/8 bit0Stop
bit
Start
bit
Start
bit
bit7/8
Stop
bit
RX
reg
Rcv buffer reg
Rcv shift
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
(RA4/RX/DT pin)
Word 3