Datasheet

PIC17C4X
DS30412C-page 84  1996 Microchip Technology Inc.
FIGURE 13-2: RCSTA REGISTER (ADDRESS: 13h, BANK 0)
R/W - 0 R/W - 0 R/W - 0 R/W - 0 U - 0 R - 0 R - 0 R - x
SPEN RX9 SREN CREN
— FERR OERR RX9D
R = Readable bit
W = Writable bit
-n = Value at POR reset
(x = unknown)
bit7 bit 0
bit 7: SPEN : Serial Port Enable bit
1 = Configures RA5/RX/DT and RA4/TX/CK pins as serial port pins
0 = Serial port disabled
bit 6: RX9 : 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5: SREN : Single Receive Enable bit
This bit enables the reception of a single byte. After receiving the byte, this bit is automatically cleared.
Synchronous mode:
1 = Enable reception
0 = Disable reception
Note: This bit is ignored in synchronous slave reception.
A
synchronous mode:
Don’t care
bit 4: CREN : Continuous Receive Enable bit
This bit enables the continuous reception of serial data.
Asynchronous mode:
1 = Enable reception
0 = Disables reception
Synchronous mode:
1 = Enables continuous reception until CREN is cleared (CREN overrides SREN)
0 = Disables continuous reception
bit 3: Unimplemented : Read as '0'
bit 2: FERR : Framing Error bit
1 = Framing error (Updated by reading RCREG)
0 = No framing error
bit 1: OERR : Overrun Error bit
1 = Overrun (Cleared by clearing CREN)
0 = No overrun error
bit 0: RX9D : 9th bit of receive data (can be the software calculated parity bit)