Datasheet
1996 Microchip Technology Inc. DS30412C-page 77
PIC17C4X
12.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR
EXTERNAL CLOCK INPUT
The use of an external clock for the PWM time-base
(Timer1 or Timer2) limits the PWM output to a maxi-
mum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when inter-
nal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, is shown in Table 12-3 (standard res-
olution mode).
12.2 Tim
er3
Timer3 is a 16-bit timer consisting of the TMR3H and
TMR3L registers. TMR3H is the high byte of the timer
and TMR3L is the low byte. This timer has an associ-
ated 16-bit period register (PR3H/CA1H:PR3L/CA1L).
This period register can be software configured to be a
second 16-bit capture register.
When the TMR3CS bit (TCON1<2>) is clear, the timer
increments every instruction cycle (Fosc/4). When
TMR3CS is set, the timer increments on every falling
edge of the RB5/TCLK3 pin. In either mode, the
TMR3ON bit must be set for the timer to increment.
When TMR3ON is clear, the timer will not increment or
set the TMR3IF bit.
Timer3 has two modes of operation, depending on the
CA1/PR3
bit (TCON2<3>). These modes are:
• One capture and one period register mode
• Dual capture register mode
The PIC17C4X has up to two 16-bit capture registers
that capture the 16-bit value of TMR3 when events are
detected on capture pins. There are two capture pins
(RB0/CAP1 and RB1/CAP2), one for each capture reg-
ister. The capture pins are multiplexed with PORTB
pins. An event can be:
• a rising edge
• a falling edge
• every 4th rising edge
• every 16th rising edge
Each 16-bit capture register has an interrupt flag asso-
ciated with it. The flag is set when a capture is made.
The capture module is truly part of the Timer3 block.
Figure 12-7 and Figure 12-8 show the block diagrams
for the two modes of operation.
TABLE 12-4: REGISTERS/BITS ASSOCIATED WITH PWM
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-on
Reset
Value on all
other
resets
(Note1)
16h, Bank 3 TCON1
CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS
0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON
0000 0000 0000 0000
10h, Bank 2 TMR1 Timer1 register
xxxx xxxx uuuu uuuu
11h, Bank 2 TMR2 Timer2 register
xxxx xxxx uuuu uuuu
16h, Bank 1 PIR
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TXIF RCIF
0000 0010 0000 0010
17h, Bank 1 PIE
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TXIE RCIE
0000 0000 0000 0000
07h, Unbanked INTSTA PEIF
T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE
0000 0000 0000 0000
06h, Unbanked CPUSTA — — STKAV GLINTD TO PD — —
--11 11-- --11 qq--
10h, Bank 3 PW1DCL DC1 DC0
— — — — — —
xx-- ---- uu-- ----
11h, Bank 3 PW2DCL DC1 DC0 TM2PW2
— — — — —
xx0- ---- uu0- ----
12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2
xxxx xxxx uuuu uuuu
13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2
xxxx xxxx uuuu uuuu
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented read as '0',
q
= value depends on conditions,
shaded cells are not used by PWM.