Datasheet

 1996 Microchip Technology Inc. DS30412C-page 33
PIC17C4X
FIGURE 6-5: PIC17C42 REGISTER FILE
MAP
Addr Unbanked
00h
INDF0
01h
FSR0
02h
PCL
03h
PCLATH
04h
ALUSTA
05h
T0STA
06h
CPUSTA
07h
INTSTA
08h
INDF1
09h
FSR1
0Ah
WREG
0Bh
TMR0L
0Ch
TMR0H
0Dh
TBLPTRL
0Eh
TBLPTRH
0Fh
BSR
Bank 0 Bank 1
(1)
Bank 2
(1)
Bank 3
(1)
10h
PORTA DDRC TMR1 PW1DCL
11h
DDRB PORTC TMR2 PW2DCL
12h
PORTB DDRD TMR3L PW1DCH
13h
RCSTA PORTD TMR3H PW2DCH
14h
RCREG DDRE PR1 CA2L
15h
TXSTA PORTE PR2 CA2H
16h
TXREG PIR PR3L/CA1L TCON1
17h
SPBRG PIE PR3H/CA1H TCON2
18h
1Fh
General
Purpose
RAM
20h
FFh
Note 1: SFR file locations 10h - 17h are banked. All
other SFRs ignore the Bank Select Register
(BSR) bits.
FIGURE 6-6: PIC17CR42/42A/43/R43/44
REGISTER FILE MAP
Addr Unbanked
00h
INDF0
01h
FSR0
02h
PCL
03h
PCLATH
04h
ALUSTA
05h
T0STA
06h
CPUSTA
07h
INTSTA
08h
INDF1
09h
FSR1
0Ah
WREG
0Bh
TMR0L
0Ch
TMR0H
0Dh
TBLPTRL
0Eh
TBLPTRH
0Fh
BSR
Bank 0 Bank 1
(1)
Bank 2
(1)
Bank 3
(1)
10h
PORTA DDRC TMR1 PW1DCL
11h
DDRB PORTC TMR2 PW2DCL
12h
PORTB DDRD TMR3L PW1DCH
13h
RCSTA PORTD TMR3H PW2DCH
14h
RCREG DDRE PR1 CA2L
15h
TXSTA PORTE PR2 CA2H
16h
TXREG PIR PR3L/CA1L TCON1
17h
SPBRG PIE PR3H/CA1H TCON2
18h
PRODL
19h
PRODH
1Ah
1Fh
General
Purpose
RAM
(2)
20h
FFh
General
Purpose
RAM
(2)
Note 1: SFR file locations 10h - 17h are banked. All
other SFRs ignore the Bank Select Register
(BSR) bits.
2: General Purpose Registers (GPR) locations
20h - FFh and 120h - 1FFh are banked. All
other GPRs ignore the Bank Select Register
(BSR) bits.