Datasheet

PIC17C4X

DS30412C-page 20  1996 Microchip Technology Inc.

Bank 2

TMR1 10h xxxx xxxx uuuu uuuu uuuu uuuu

TMR2 11h xxxx xxxx uuuu uuuu uuuu uuuu

TMR3L 12h xxxx xxxx uuuu uuuu uuuu uuuu

TMR3H 13h xxxx xxxx uuuu uuuu uuuu uuuu

PR1 14h xxxx xxxx uuuu uuuu uuuu uuuu

PR2 15h xxxx xxxx uuuu uuuu uuuu uuuu

PR3/CA1L 16h xxxx xxxx uuuu uuuu uuuu uuuu

PR3/CA1H 17h xxxx xxxx uuuu uuuu uuuu uuuu

Bank 3

PW1DCL 10h xx-- ---- uu-- ---- uu-- ----

PW2DCL 11h xx-- ---- uu-- ---- uu-- ----

PW1DCH 12h xxxx xxxx uuuu uuuu uuuu uuuu

PW2DCH 13h xxxx xxxx uuuu uuuu uuuu uuuu

CA2L 14h xxxx xxxx uuuu uuuu uuuu uuuu

CA2H 15h xxxx xxxx uuuu uuuu uuuu uuuu

TCON1 16h 0000 0000 0000 0000 uuuu uuuu

TCON2 17h 0000 0000 0000 0000 uuuu uuuu

Unbanked

PRODL

(5)

18h xxxx xxxx uuuu uuuu uuuu uuuu

PRODH

(5)

19h xxxx xxxx uuuu uuuu uuuu uuuu

TABLE 4-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)

MCLR

Reset

WDT Reset

Wake-up from SLEEP

through interrupt

Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.

Note 1: One or more bits in INTSTA, PIR will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt

vector.

3: See Table 4-3 for reset value of speciﬁc condition.

4: Only applies to the PIC17C42.

5: Does not apply to the PIC17C42.