Datasheet

 1996 Microchip Technology Inc. DS30412C-page 19
PIC17C4X
TABLE 4-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS
Register Address Power-on Reset
MCLR
Reset
WDT Reset
Wake-up from SLEEP
through interrupt
Unbanked
INDF0 00h 0000 0000 0000 0000 0000 0000
FSR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h 0000h 0000h
PC + 1
(2)
PCLATH 03h 0000 0000 0000 0000 uuuu uuuu
ALUSTA 04h 1111 xxxx 1111 uuuu 1111 uuuu
T0STA 05h 0000 000- 0000 000- 0000 000-
CPUSTA
(3)
06h --11 11-- --11 qq-- --uu qq--
INTSTA 07h 0000 0000 0000 0000
uuuu uuuu
(1)
INDF1 08h 0000 0000 0000 0000 uuuu uuuu
FSR1 09h xxxx xxxx uuuu uuuu uuuu uuuu
WREG 0Ah xxxx xxxx uuuu uuuu uuuu uuuu
TMR0L 0Bh xxxx xxxx uuuu uuuu uuuu uuuu
TMR0H 0Ch xxxx xxxx uuuu uuuu uuuu uuuu
TBLPTRL
(4)
0Dh xxxx xxxx uuuu uuuu uuuu uuuu
TBLPTRH
(4)
0Eh xxxx xxxx uuuu uuuu uuuu uuuu
TBLPTRL
(5)
0Dh 0000 0000 0000 0000 uuuu uuuu
TBLPTRH
(5)
0Eh 0000 0000 0000 0000 uuuu uuuu
BSR 0Fh 0000 0000 0000 0000 uuuu uuuu
Bank 0
PORTA 10h 0-xx xxxx 0-uu uuuu uuuu uuuu
DDRB 11h 1111 1111 1111 1111 uuuu uuuu
PORTB 12h xxxx xxxx uuuu uuuu uuuu uuuu
RCSTA 13h 0000 -00x 0000 -00u uuuu -uuu
RCREG 14h xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA 15h 0000 --1x 0000 --1u uuuu --uu
TXREG 16h xxxx xxxx uuuu uuuu uuuu uuuu
SPBRG 17h xxxx xxxx uuuu uuuu uuuu uuuu
Bank 1
DDRC 10h 1111 1111 1111 1111 uuuu uuuu
PORTC 11h xxxx xxxx uuuu uuuu uuuu uuuu
DDRD 12h 1111 1111 1111 1111 uuuu uuuu
PORTD 13h xxxx xxxx uuuu uuuu uuuu uuuu
DDRE 14h ---- -111 ---- -111 ---- -uuu
PORTE 15h ---- -xxx ---- -uuu ---- -uuu
PIR 16h 0000 0010 0000 0010
uuuu uuuu
(1)
PIE 17h 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition.
Note 1: One or more bits in INTSTA, PIR will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 4-3 for reset value of specific condition.
4: Only applies to the PIC17C42.
5: Does not apply to the PIC17C42.