Datasheet

 1996 Microchip Technology Inc. DS30412C-page 189
PIC17C4X
Applicable Devices 42 R42 42A 43 R43 44
FIGURE 19-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 19-9: SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 19-10: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 19-10: SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No. Sym Characteristic Min Typ† Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC17CR42/42A/43/R43/44 — — 50 ns
PIC17LCR42/42A/43/R43/44 — — 75 ns
121 TckRF Clock out rise time and fall time
(Master Mode)
PIC17CR42/42A/43/R43/44 — — 25 ns
PIC17LCR42/42A/43/R43/44 — — 40 ns
122 TdtRF Data out rise time and fall time PIC17CR42/42A/43/R43/44 — — 25 ns
PIC17LCR42/42A/43/R43/44 — — 40 ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Parameter
No. Sym Characteristic Min Typ† Max Units Conditions
125 TdtV2ckL SYNC RCV (MASTER & SLA
VE)
Data hold before CK↓ (DT hold time)
15 — — ns
126 TckL2dtl Data hold after CK↓ (DT hold time) 15 — — ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
121
121
120
122
RA5/TX/CK
RA4/RX/DT
pin
pin
125
126
RA5/TX/CK
RA4/RX/DT
pin
pin