Datasheet

 1996 Microchip Technology Inc. DS30412C-page 15
PIC17C4X
4.0 RESET
The PIC17CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR
reset during normal operation
• WDT Reset (normal operation)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are forced to a “reset
state” on Power-on Reset (POR), on MCLR
or WDT
Reset and on M
CLR reset during SLEEP. They are not
affected by a WDT Reset during SLEEP, since this reset
is viewed as the resumption of normal operation. The
T
O and PD bits are set or cleared differently in different
reset situations as indicated in Table 4-3. These bits are
used in software to determine the nature of reset. See
Table 4-4 for a full description of reset states of all reg-
isters.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 4-1.
Note: While the device is in a reset state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE
and RE2/WR
pins as high outputs.
4.1 P
ower-on Reset (POR), Power-up
Timer (PWRT), and Oscillator Start-up
Timer (OST)
4.1.1 POWER-ON RESET (POR)
The Power-on Reset circuit holds the device in reset
until V
DD
is above the trip point (in the range of 1.4V -
2.3V). The PIC17C42 does not produce an internal
reset when V
DD
declines. All other devices will produce
an internal reset for both rising and falling V DD . To take
advantage of the POR, just tie the MCLR
/V PP
pin
directly (or through a resistor) to V
DD
. This will eliminate
external RC components usually needed to create
Power-on Reset. A minimum rise time for V
DD
is
required. See Electrical Specifications for details.
4.1.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 96 ms time-out
(nominal) on power-up. This occurs from rising edge of
the POR signal and after the first rising edge of MCLR
(detected high). The Power-up Timer operates on an
internal RC oscillator. The chip is kept in RESET as
long as the PWRT is active. In most cases the PWRT
delay allows the V
DD
to rise to an acceptable level.
The power-up time delay will vary from chip to chip and
to V
DD
and temperature. See DC parameters for
details.
FIGURE 4-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
Reset
MCLR
VDD
OSC1
WDT
Module
V
DD rise
detect
OST/PWRT
On-chip
RC OSC†
WDT
Time_Out
Power_On_Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Power_Up
(Enable the PWRT timer
only during Power_Up)
(Power_Up + Wake_Up) (XT + LF)
(Enable the OST if it is Power_Up or Wake_Up
from SLEEP and OSC type is XT or LF)
Reset
Enable OST
Enable PWRT
† This RC oscillator is shared with the WDT
when not in a power-up sequence.
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