Datasheet

PIC17C4X
DS30412C-page 120  1996 Microchip Technology Inc.
CPFSLT
Compare f with WREG,
skip if f < WREG
Syntax: [
label ] CPFSLT f
Operands: 0 ≤ f ≤ 255
Operation:
(f) – (WREG),
skip if (f) < (WREG)
(unsigned comparison)
Status Affected: None
Encoding:
0011 0000 ffff ffff
Description:
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If the contents of 'f' < the contents of
WREG, then the fetched instruction is
discarded and an NOP is executed
instead making this a two-cycle instruc-
tion.
Words: 1
Cycles: 1 (2)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Execute NOP
If skip:
Q1 Q2 Q3 Q4
Forced NOP NOP Execute NOP
Example:
HERE CPFSLT REG
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG < WREG;
PC = Address (LESS)
If REG ≥ WREG;
PC = Address (NLESS)
DAW Decimal Adjust WREG Register
Syntax: [
label ] DAW f,s
Operands: 0 ≤ f ≤ 255
s ∈ [0,1]
Operation:
If [WREG<3:0> >9] .OR. [DC = 1] then
WREG<3:0> + 6 → f<3:0>, s<3:0>;
else
WREG<3:0> → f<3:0>, s<3:0>;
If [WREG<7:4> >9] .OR. [C = 1] then
WREG<7:4> + 6 → f<7:4>, s<7:4>
else
WREG<7:4> → f<7:4>, s<7:4>
Status Affected: C
Encoding:
0010 111s ffff ffff
Description:
DAW adjusts the eight bit value in
WREG resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0: Result is placed in Data
memory location 'f' and
WREG.
s = 1: Result is placed in Data
memory location 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Execute Write
register 'f'
and other
specified
register
Example1:
DAW REG1, 0
Before Instruction
WREG = 0xA5
REG1 = ??
C=0
DC = 0
After Instruction
WREG = 0x05
REG1 = 0x05
C=1
DC = 0
Example 2:
Before Instruction
WREG = 0xCE
REG1 = ??
C=0
DC = 0
After Instruction
WREG = 0x24
REG1 = 0x24
C=1
DC = 0