PIC17C4X High-Performance 8-Bit CMOS EPROM/ROM Microcontroller Devices included in this data sheet: PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 PIC17C44 PIC17C42† PDIP, CERDIP, Windowed CERDIP Microcontroller Core Features: ✯ • Only 58 single word instructions to learn • All single cycle instructions (121 ns) except for program branches and table reads/writes which are two-cycle • Operating speed: - DC - 33 MHz clock input - DC - 121 ns instruction cycle Program Memory Device Data Memory EPROM ✯ ROM PIC1
PIC17C4X MQFP TQFP 39 38 37 36 35 34 33 32 31 30 29 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 MCLR/VPP VSS VSS RE0/ALE RE1/OE RE2/WR TEST 28 27 26 25 24 23 22 21 20 19 18 TEST RE2/WR RE1/OE RE0/ALE VSS VSS MCLR/VPP RD7/AD15 RD6/AD14 RD5/AD13 RD4/AD12 1 2 3 4 5 6 7 8 9 10 11 PIC17C4X 7 8 9 10 11 12 13 14 15 16 17 PIC17C4X RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7 VSS VSS RB0/CAP1 RB1/CAP2 RB2/PWM1 RB3/PWM2 RB4/TCLK12 44 43 42 41 40 39 38 37 36 35 34 6 5 4 3 2 1 44 43 42 41 40 PLCC RA0/INT RA1/T0CKI RA2 RA3 RA4/
PIC17C4X Table of Contents 1.0 Overview .............................................................................................................................................................. 5 2.0 PIC17C4X Device Varieties ................................................................................................................................. 7 3.0 Architectural Overview ..........................................................................................................................
PIC17C4X NOTES: DS30412C-page 4 1996 Microchip Technology Inc.
PIC17C4X 1.0 OVERVIEW This data sheet covers the PIC17C4X group of the PIC17CXX family of microcontrollers. The following devices are discussed in this data sheet: • • • • • • PIC17C42 PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 PIC17C44 There are four configuration options for the device operational modes: • • • • The PIC17CR42, PIC17C42A, PIC17C43, PIC17CR43, and PIC17C44 devices include architectural enhancements over the PIC17C42. These enhancements will be discussed throughout this data sheet.
PIC17C4X TABLE 1-1: PIC17CXX FAMILY OF DEVICES Features PIC17C42 PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 PIC17C44 Maximum Frequency of Operation Operating Voltage Range Program Memory x16 (EPROM) (ROM) Data Memory (bytes) Hardware Multiplier (8 x 8) Timer0 (16-bit + 8-bit postscaler) Timer1 (8-bit) Timer2 (8-bit) Timer3 (16-bit) Capture inputs (16-bit) PWM outputs (up to 10-bit) USART/SCI Power-on Reset Watchdog Timer External Interrupts Interrupt Sources Program Memory Code Protect I/O Pins I/O Hig
PIC17C4X 2.0 PIC17C4X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC17C4X Product Selection System section at the end of this data sheet. When placing orders, please use the “PIC17C4X Product Identification System” at the back of this data sheet to specify the correct part number.
PIC17C4X NOTES: DS30412C-page 8 1996 Microchip Technology Inc.
PIC17C4X 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC17C4X can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC17C4X uses a modified Harvard architecture. This architecture has the program and data accessed from separate memories. So the device has a program memory bus and a data memory bus.
DS30412C-page 10 RA0/INT RA1/T0CKI RA2 RA3 RA4/RX/DT RA5/TX/CK PORTA RB0/CAP1 RB1/CAP2 RB2/PWM1 RB2/PWM2 RB4/TCLK12 RB5/TCLK3 RB6 RB7 PORTB 6 8 SHIFTER ALU 2 6 8 6 RA1/ T0CKI BITOP DATA BUS <8> RDF RA0/INT RA1/T0CKI PERIPHERALS Timer0 MODULE SERIAL PORT DIGITAL I/O PORTS A, B Timer1, Timer2, Timer3 CAPTURE PWM WREG <8> WRF READ/WRITE DECODE FOR REGISTERS MAPPED IN DATA SPACE IR <7> BSR 4 DATA LATCH DATA RAM 232x8 IR <2:0> 3 IR BUS <7:0> RAM ADDR BUFFER 8 INTERRUPT MODULE
1996 Microchip Technology Inc.
PIC17C4X TABLE 3-1: PINOUT DESCRIPTIONS DIP No. PLCC No. QFP No.
PIC17C4X TABLE 3-1: PINOUT DESCRIPTIONS Name DIP No. PLCC No. QFP No. I/O/P Buffer Description Type Type RD0/AD8 RD1/AD9 RD2/AD10 RD3/AD11 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 40 39 38 37 36 35 34 33 43 42 41 40 39 38 37 36 15 14 13 12 11 10 9 8 I/O I/O I/O I/O I/O I/O I/O I/O TTL TTL TTL TTL TTL TTL TTL TTL RE0/ALE 30 32 4 I/O TTL RE1/OE 29 31 3 I/O TTL RE2/WR 28 30 2 I/O TTL TEST 27 29 1 I ST VSS 10, 31 PORTD is a bi-directional I/O Port.
PIC17C4X Clocking Scheme/Instruction Cycle 3.1 3.2 The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 3-3.
PIC17C4X 4.0 RESET 4.1 Power-on Reset (POR), Power-up Timer (PWRT), and Oscillator Start-up Timer (OST) 4.1.1 POWER-ON RESET (POR) The PIC17CXX differentiates between various kinds of reset: • Power-on Reset (POR) • MCLR reset during normal operation • WDT Reset (normal operation) Some registers are not affected in any reset condition; their status is unknown on POR and unchanged in any other reset.
PIC17C4X 4.1.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (1024TOSC) delay after MCLR is detected high or a wake-up from SLEEP event occurs. TABLE 4-1: Oscillator Configuration Power-up Wake up from SLEEP MCLR Reset XT, LF Greater of: 96 ms or 1024TOSC 1024TOSC — EC, RC Greater of: 96 ms or 1024TOSC — — The OST time-out is invoked only for XT and LF oscillator modes on a Power-on Reset or a Wake-up from SLEEP.
PIC17C4X FIGURE 4-2: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-4: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 1996 Microchip Technology Inc.
PIC17C4X FIGURE 4-5: OSCILLATOR START-UPTIME FIGURE 4-8: PIC17C42 EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD VDD VDD MCLR D R OSC2 R1 MCLR TOSC1 PIC17C42 C TOST OST TIME_OUT PWRT TIME_OUT TPWRT INTERNAL RESET This figure shows in greater detail the timings involved with the oscillator start-up timer. In this example the low frequency crystal start-up time is larger than power-up time (TPWRT).
PIC17C4X TABLE 4-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS MCLR Reset WDT Reset Wake-up from SLEEP through interrupt Register Address Power-on Reset Unbanked INDF0 FSR0 PCL 00h 01h 02h 0000 0000 xxxx xxxx 0000h 0000 0000 uuuu uuuu 0000h 03h 04h 05h 06h 0000 1111 0000 --11 0000 1111 0000 --11 07h 0000 0000 0000 0000 08h 09h 0Ah 0Bh 0Ch 0Dh 0000 xxxx xxxx xxxx xxxx xxxx 0000 uuuu uuuu uuuu uuuu uuuu TBLPTRH (4) 0Eh xxxx xxxx uuuu uuuu uuuu uuuu (5) 0Dh 0000 0000 00
PIC17C4X TABLE 4-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS Power-on Reset MCLR Reset WDT Reset (Cont.
PIC17C4X 5.0 INTERRUPTS The PIC17C4X devices have 11 sources of interrupt: • • • • • • • • • • • External interrupt from the RA0/INT pin Change on RB7:RB0 pins TMR0 Overflow TMR1 Overflow TMR2 Overflow TMR3 Overflow USART Transmit buffer empty USART Receive buffer full Capture1 Capture2 T0CKI edge occurred There are four registers used in the control and status of interrupts. These are: • • • • CPUSTA INTSTA PIE PIR The CPUSTA register contains the GLINTD bit. This is the Global Interrupt Disable bit.
PIC17C4X 5.1 Interrupt Status Register (INTSTA) The Interrupt Status/Control register (INTSTA) records the individual interrupt requests in flag bits, and contains the individual interrupt enable bits (not for the peripherals). The PEIF bit is a read only, bit wise OR of all the peripheral flag bits in the PIR register (Figure 5-4).
PIC17C4X 5.2 Peripheral Interrupt Enable Register (PIE) This register contains the individual flag bits for the Peripheral interrupts.
PIC17C4X 5.3 Peripheral Interrupt Request Register (PIR) Note: This register contains the individual flag bits for the peripheral interrupts. These bits will be set by the specified condition, even if the corresponding interrupt enable bit is cleared (interrupt disabled), or the GLINTD bit is set (all interrupts disabled). Before enabling an interrupt, the user may wish to clear the interrupt flag to ensure that the program does not immediately branch to the peripheral interrupt service routine.
PIC17C4X 5.4 Interrupt Operation Global Interrupt Disable bit, GLINTD (CPUSTA<4>), enables all unmasked interrupts (if clear) or disables all interrupts (if set). Individual interrupts can be disabled through their corresponding enable bits in the INTSTA register. Peripheral interrupts need either the global peripheral enable PEIE bit disabled, or the specific peripheral enable bit disabled. Disabling the peripherals via the global peripheral enable bit, disables all peripheral interrupts.
PIC17C4X 5.5 RA0/INT Interrupt 5.7 The external interrupt on the RA0/INT pin is edge triggered. Either the rising edge, if INTEDG bit (T0STA<7>) is set, or the falling edge, if INTEDG bit is clear. When a valid edge appears on the RA0/INT pin, the INTF bit (INTSTA<4>) is set. This interrupt can be disabled by clearing the INTE control bit (INTSTA<0>). The INT interrupt can wake the processor from SLEEP. See Section 14.4 for details on SLEEP operation. 5.
PIC17C4X 5.9 Context Saving During Interrupts During an interrupt, only the returned PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt; e.g. WREG, ALUSTA and the BSR registers. This requires implementation in software. EXAMPLE 5-1: Example 5-1 shows the saving and restoring of information for an interrupt service routine. The PUSH and POP routines could either be in each interrupt service routine or could be subroutines that were called.
PIC17C4X NOTES: DS30412C-page 28 1996 Microchip Technology Inc.
PIC17C4X 6.0 MEMORY ORGANIZATION There are two memory blocks in the PIC17C4X; program memory and data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into General Purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here.
PIC17C4X MODE MEMORY ACCESS Internal Program Memory Configuration Bits, Test Memory, Boot ROM Microprocessor No Access No Access Microcontroller Access Access Extended Microcontroller Access No Access Protected Microcontroller Access Access MEMORY MAP IN DIFFERENT MODES PIC17C42, PIC17CR42, PIC17C42A Extended Microcontroller Mode Microcontroller Modes 0000h 0000h 0000h 07FFh On-chip Program Memory 07FFh 0800h On-chip Program Memory PROGRAM SPACE Microprocessor Mode 0800h External
PIC17C4X 6.1.2 EXTERNAL MEMORY INTERFACE In extended microcontroller mode, when the device is executing out of internal memory, the control signals will continue to be active. That is, they indicate the action that is occurring in the internal memory. The external memory access is ignored. When either microprocessor or extended microcontroller mode is selected, PORTC, PORTD and PORTE are configured as the system bus.
PIC17C4X 6.2 Data Memory Organization 6.2.1 GENERAL PURPOSE REGISTER (GPR) Data memory is partitioned into two areas. The first is the General Purpose Registers (GPR) area, while the second is the Special Function Registers (SFR) area. The SFRs control the operation of the device. All devices have some amount of GPR area. The GPRs are 8-bits wide. When the GPR area is greater than 232, it must be banked to allow access to the additional memory space.
PIC17C4X FIGURE 6-5: PIC17C42 REGISTER FILE MAP FIGURE 6-6: PIC17CR42/42A/43/R43/44 REGISTER FILE MAP Addr Unbanked Addr Unbanked 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh INDF0 FSR0 PCL PCLATH ALUSTA T0STA CPUSTA INTSTA INDF1 FSR1 WREG TMR0L TMR0H TBLPTRL TBLPTRH BSR Bank 0 10h 11h 12h 13h 14h 15h 16h 17h 18h 1Fh 20h Bank 1 (1) Bank 2 (1) Bank 3 (1) PORTA DDRC TMR1 PW1DCL DDRB PORTC TMR2 PW2DCL POR
PIC17C4X TABLE 6-3: Address Name SPECIAL FUNCTION REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (3) ---- ---- Unbanked 00h INDF0 Uses contents of FSR0 to address data memory (not a physical register) ---- ---- 01h FSR0 Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 02h PCL Low order 8-bits of PC 0000 0000 0000 0000 03h(1) PCLATH Holding register for upper 8-bits of PC 04h ALUSTA 05h T0STA 0000 0000
PIC17C4X TABLE 6-3: Address SPECIAL FUNCTION REGISTERS (Cont.
PIC17C4X 6.2.2.1 ALU STATUS REGISTER (ALUSTA) The ALUSTA register contains the status bits of the Arithmetic and Logic Unit and the mode control bits for the indirect addressing register. As with all the other registers, the ALUSTA register can be the destination for any instruction. If the ALUSTA register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC17C4X 6.2.2.2 CPU STATUS REGISTER (CPUSTA) The CPUSTA register contains the status and control bits for the CPU. This register is used to globally enable/disable interrupts. If only a specific interrupt is desired to be enabled/disabled, please refer to the INTerrupt STAtus (INTSTA) register and the Peripheral Interrupt Enable (PIE) register. This register also indicates if the stack is available and contains the Power-down (PD) and Time-out (TO) bits. The TO, PD, and STKAV bits are not writable.
PIC17C4X 6.2.2.3 TMR0 STATUS/CONTROL REGISTER (T0STA) This register contains various control bits. Bit7 (INTEDG) is used to control the edge upon which a signal on the RA0/INT pin will set the RB0/INT interrupt flag. The other bits configure the Timer0 prescaler and clock source. (Figure 11-1).
PIC17C4X 6.3 Stack Operation 6.4 Indirect Addressing The PIC17C4X devices have a 16 x 16-bit wide hardware stack (Figure 6-1). The stack is not part of either the program or data memory space, and the stack pointer is neither readable nor writable. The PC is “PUSHed” onto the stack when a CALL instruction is executed or an interrupt is acknowledged. The stack is “POPed” in the event of a RETURN, RETLW, or a RETFIE instruction execution. PCLATH is not affected by a “PUSH” or a “POP” operation.
PIC17C4X 6.4.1 INDIRECT ADDRESSING REGISTERS The PIC17C4X has four registers for indirect addressing. These registers are: A simple program to clear RAM from 20h - FFh is shown in Example 6-1. EXAMPLE 6-1: • INDF0 and FSR0 • INDF1 and FSR1 Registers INDF0 and INDF1 are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data.
PIC17C4X 6.7 Program Counter Module Using Figure 6-11, the operations of the PC and PCLATH for different instructions are as follows: The Program Counter (PC) is a 16-bit register. PCL, the low byte of the PC, is mapped in the data memory. PCL is readable and writable just as is any other register. PCH is the high byte of the PC and is not directly addressable.
PIC17C4X 6.8 Bank Select Register (BSR) For the PIC17C43, PIC17CR43, and PIC17C44 devices, the need for a large general purpose memory space dictated a general purpose RAM banking scheme. The upper nibble of the BSR selects the currently active general purpose RAM bank. To assist this, a MOVLR bank instruction has been provided in the instruction set. The BSR is used to switch between banks in the data memory area (Figure 6-13).
PIC17C4X 7.0 TABLE READS AND TABLE WRITES FIGURE 7-2: The PIC17C4X has four instructions that allow the processor to move data from the data memory space to the program memory space, and vice versa. Since the program memory space is 16-bits wide and the data memory space is 8-bits wide, two operations are required to move 16-bit values to/from the data memory. The TLWT t,f and TABLWT t,i,f instructions are used to write data from the data memory space to the program memory space.
PIC17C4X FIGURE 7-3: TLRD INSTRUCTION OPERATION FIGURE 7-4: TABLE POINTER TABLE POINTER TBLPTRH TBLPTRH TBLPTRL TLRD 1,f TBLPTRL TABLE LATCH (16-bit) TABLE LATCH (16-bit) TABLATH TABLRD INSTRUCTION OPERATION TABLATH TABLATL TLRD TABLATL 0,f 3 3 DATA MEMORY TABLRD TABLRD 1,i,f DATA MEMORY f 0,i,f PROGRAM MEMORY PROGRAM MEMORY 1 f 1 Prog-Mem (TBLPTR) 2 Note 1: 8-bit value, from TABLAT (16-bit) high or low byte, loaded into register 'f'.
PIC17C4X Table Writes to Internal Memory 7.1 7.1.1 An interrupt source or reset are the only events that terminate a long write operation. Terminating the long write from an interrupt source requires that the interrupt enable and flag bits are set. The GLINTD bit only enables the vectoring to the interrupt address. A table write operation to internal memory causes a long write operation. The long write is necessary for programming the internal EPROM.
PIC17C4X 7.2 Table Writes to External Memory 7.2.2 Table writes to external memory are always two-cycle instructions. The second cycle writes the data to the external memory location. The sequence of events for an external memory write are the same for an internal write. TABLE WRITE CODE The “i” operand of the TABLWT instruction can specify that the value in the 16-bit TBLPTR register is automatically incremented for the next write. In Example 7-1, the TBLPTR register is not automatically incremented.
PIC17C4X FIGURE 7-6: CONSECUTIVE TABLWT WRITE TIMING (EXTERNAL MEMORY) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 AD15:AD0 PC Instruction fetched TABLWT1 Instruction executed INST (PC-1) PC+1 TBL1 Data out 1 TABLWT2 PC+2 TBL2 Data out 2 INST (PC+2) INST (PC+3) TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2 Data write cycle PC+3 INST (PC+2) Data write cycle ALE OE WR 1996 Microchip Technology Inc.
PIC17C4X 7.3 Table Reads EXAMPLE 7-2: The table read allows the program memory to be read. This allows constant data to be stored in the program memory space, and retrieved into data memory when needed. Example 7-2 reads the 16-bit value at program memory address TBLPTR. After the dummy byte has been read from the TABLATH, the TABLATH is loaded with the 16-bit data from program memory address TBLPTR + 1.
PIC17C4X 8.0 HARDWARE MULTIPLIER Example 8-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument’s most significant bit (MSb) is tested and the appropriate subtractions are done. All PIC17C4X devices except the PIC17C42, have an 8 x 8 hardware multiplier included in the ALU of the device. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC17C4X Example 8-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in 4 registers RES3:RES0.
PIC17C4X Example 8-4 shows the sequence to do an 16 x 16 signed multiply. Equation 8-2 shows the algorithm that used. The 32-bit result is stored in four registers RES3:RES0. To account for the sign bits of the arguments, each argument pairs most significant bit (MSb) is tested and the appropriate subtractions are done.
PIC17C4X NOTES: DS30412C-page 52 1996 Microchip Technology Inc.
PIC17C4X 9.0 I/O PORTS The PIC17C4X devices have five I/O ports, PORTA through PORTE. PORTB through PORTE have a corresponding Data Direction Register (DDR), which is used to configure the port pins as inputs or outputs. These five ports are made up of 33 I/O pins. Some of these ports pins are multiplexed with alternate functions. PORTC, PORTD, and PORTE are multiplexed with the system bus.
PIC17C4X FIGURE 9-2: RA2 AND RA3 BLOCK DIAGRAM FIGURE 9-3: RA4 AND RA5 BLOCK DIAGRAM Data Bus Serial port input signal Data Bus Q Q D RD_PORTA (Q2) RD_PORTA (Q2) CK Serial port output signals WR_PORTA (Q4) OE = SPEN,SYNC,TXEN, CREN, SREN for RA4 Note: I/O pins have protection diodes to VSS. OE = SPEN (SYNC+SYNC,CSRC) for RA5 Note: I/O pins have protection diodes to VDD and VSS.
PIC17C4X 9.2 PORTB and DDRB Registers This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt by: PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is DDRB. A '1' in DDRB configures the corresponding port pin as an input. A '0' in the DDRB register configures the corresponding port pin as an output. Reading PORTB reads the status of the pins, whereas writing to it will write to the port latch.
PIC17C4X FIGURE 9-5: BLOCK DIAGRAM OF RB3 AND RB2 PORT PINS Peripheral Data in RBPU (PORTA<7>) Weak Pull-Up Match Signal from other port pins RBIF Port Input Latch Data Bus RD_DDRB (Q2) RD_PORTB (Q2) D OE Q WR_DDRB (Q4) CK D Port Data Q CK R WR_PORTB (Q4) PWM_output PWM_select Note: I/O pins have protection diodes to VDD and Vss. DS30412C-page 56 1996 Microchip Technology Inc.
PIC17C4X Example 9-1 shows the instruction sequence to initialize PORTB. The Bank Select Register (BSR) must be selected to Bank 0 for the port to be initialized.
PIC17C4X 9.3 PORTC and DDRC Registers Example 9-2 shows the instruction sequence to initialize PORTC. The Bank Select Register (BSR) must be selected to Bank 1 for the port to be initialized. PORTC is an 8-bit bi-directional port. The corresponding data direction register is DDRC. A '1' in DDRC configures the corresponding port pin as an input. A '0' in the DDRC register configures the corresponding port pin as an output.
PIC17C4X TABLE 9-5: PORTC FUNCTIONS Name Bit Buffer Type Function RC0/AD0 bit0 TTL Input/Output or system bus address/data pin. RC1/AD1 bit1 TTL Input/Output or system bus address/data pin. RC2/AD2 bit2 TTL Input/Output or system bus address/data pin. RC3/AD3 bit3 TTL Input/Output or system bus address/data pin. RC4/AD4 bit4 TTL Input/Output or system bus address/data pin. RC5/AD5 bit5 TTL Input/Output or system bus address/data pin.
PIC17C4X 9.4 PORTD and DDRD Registers Example 9-3 shows the instruction sequence to initialize PORTD. The Bank Select Register (BSR) must be selected to Bank 1 for the port to be initialized. PORTD is an 8-bit bi-directional port. The corresponding data direction register is DDRD. A '1' in DDRD configures the corresponding port pin as an input. A '0' in the DDRC register configures the corresponding port pin as an output.
PIC17C4X TABLE 9-7: Name PORTD FUNCTIONS Bit Buffer Type RD0/AD8 bit0 RD1/AD9 bit1 RD2/AD10 bit2 RD3/AD11 bit3 RD4/AD12 bit4 RD5/AD13 bit5 RD6/AD14 bit6 RD7/AD15 bit7 Legend: TTL = TTL input. TABLE 9-8: TTL TTL TTL TTL TTL TTL TTL TTL Function Input/Output or system bus address/data pin. Input/Output or system bus address/data pin. Input/Output or system bus address/data pin. Input/Output or system bus address/data pin. Input/Output or system bus address/data pin.
PIC17C4X 9.4.1 PORTE AND DDRE REGISTER Example 9-4 shows the instruction sequence to initialize PORTE. The Bank Select Register (BSR) must be selected to Bank 1 for the port to be initialized. PORTE is a 3-bit bi-directional port. The corresponding data direction register is DDRE. A '1' in DDRE configures the corresponding port pin as an input. A '0' in the DDRE register configures the corresponding port pin as an output.
PIC17C4X TABLE 9-9: PORTE FUNCTIONS Name Bit Buffer Type RE0/ALE bit0 RE1/OE bit1 RE2/WR bit2 Legend: TTL = TTL input. TABLE 9-10: Address TTL TTL TTL Function Input/Output or system bus Address Latch Enable (ALE) control pin. Input/Output or system bus Output Enable (OE) control pin. Input/Output or system bus Write (WR) control pin.
PIC17C4X 9.5 I/O Programming Considerations 9.5.1 BI-DIRECTIONAL I/O PORTS EXAMPLE 9-5: Any instruction which writes, operates internally as a read followed by a write operation. For example, the BCF and BSF instructions read the register into the CPU, execute the bit operation, and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PIC17C4X 10.0 OVERVIEW OF TIMER RESOURCES The PIC17C4X has four timer modules. Each module can generate an interrupt to indicate that an event has occurred. These timers are called: • Timer0 - 16-bit timer with programmable 8-bit prescaler • Timer1 - 8-bit timer • Timer2 - 8-bit timer • Timer3 - 16-bit timer For enhanced time-base functionality, two input Captures and two Pulse Width Modulation (PWM) outputs are possible.
PIC17C4X NOTES: DS30412C-page 66 1996 Microchip Technology Inc.
PIC17C4X 11.0 TIMER0 The Timer0 module consists of a 16-bit timer/counter, TMR0. The high byte is TMR0H and the low byte is TMR0L. A software programmable 8-bit prescaler makes an effective 24-bit overflow timer. The clock source is also software programmable as either the internal instruction clock or the RA1/T0CKI pin. The control bits for this module are in register T0STA (Figure 11-1).
PIC17C4X 11.1 Timer0 Operation 11.2 When the T0CS (T0STA<5>) bit is set, TMR0 increments on the internal clock. When T0CS is clear, TMR0 increments on the external clock (RA1/T0CKI pin). The external clock edge can be configured in software. When the T0SE (T0STA<6>) bit is set, the timer will increment on the rising edge of the RA1/T0CKI pin. When T0SE is clear, the timer will increment on the falling edge of the RA1/T0CKI pin. The prescaler can be programmed to introduce a prescale of 1:1 to 1:256.
PIC17C4X Read/Write Consideration for TMR0 11.3 11.3.2 Since writing to either TMR0L or TMR0H will effectively inhibit increment of that half of the TMR0 in the next cycle (following write), but not inhibit increment of the other half, the user must write to TMR0L first and TMR0H next in two consecutive instructions, as shown in Example 11-2. The interrupt must be disabled. Any write to either TMR0L or TMR0H clears the prescaler.
PIC17C4X FIGURE 11-5: TMR0 READ/WRITE IN TIMER MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 AD15:AD0 ALE WR_TRM0L WR_TMR0H RD_TMR0L TMR0L Instruction fetched Instruction executed 12 12 TMR0H FE 56 FF MOVFP MOVFP DATAL,TMR0L DATAH,TMR0H Write TMR0L Write TMR0H Previously Fetched Instruction AB 13 57 MOVPF TMR0L,W Read TMR0L MOVFP MOVFP DATAL,TMR0L DATAH,TMR0H Write TMR0L Write TMR0H MOVPF TMR0L,W Read TMR0L MOVPF TMR0L,W Read TMR0L 58 MOVPF
PIC17C4X 12.0 TIMER1, TIMER2, TIMER3, PWMS AND CAPTURES The PIC17C4X has a wealth of timers and time-based functions to ease the implementation of control applications. These time-base functions include two PWM outputs and two Capture inputs. Timer1 and Timer2 are two 8-bit incrementing timers, each with a period register (PR1 and PR2 respectively) and separate overflow interrupt flags.
PIC17C4X FIGURE 12-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3) R-0 R-0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON bit7 bit0 R = Readable bit W = Writable bit -n = Value at POR reset bit 7: CA2OVF: Capture2 Overflow Status bit This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L) before the next capture event occurred.
PIC17C4X 12.1 Timer1 and Timer2 12.1.1 TIMER1, TIMER2 IN 8-BIT MODE 12.1.1.1 Both Timer1 and Timer2 will operate in 8-bit mode when the T16 bit is clear. These two timers can be independently configured to increment from the internal instruction cycle clock or from an external clock source on the RB4/TCLK12 pin. The timer clock source is configured by the TMRxCS bit (x = 1 for Timer1 or = 2 for Timer2).
PIC17C4X 12.1.2 12.1.2.1 TIMER1 & TIMER2 IN 16-BIT MODE To select 16-bit mode, the T16 bit must be set. In this mode TMR1 and TMR2 are concatenated to form a 16-bit timer (TMR2:TMR1). The 16-bit timer increments until it matches the 16-bit period register (PR2:PR1). On the following timer clock, the timer value is reset to 0h, and the TMR1IF bit is set. EXTERNAL CLOCK INPUT FOR TMR1:TMR2 When TMR1CS is set, the 16-bit TMR2:TMR1 increments on the falling edge of clock input TCLK12.
PIC17C4X 12.1.3 FIGURE 12-5: SIMPLIFIED PWM BLOCK DIAGRAM USING PULSE WIDTH MODULATION (PWM) OUTPUTS WITH TMR1 AND TMR2 Two high speed pulse width modulation (PWM) outputs are provided. The PWM1 output uses Timer1 as its time-base, while PWM2 may be software configured to use either Timer1 or Timer2 as the time-base. The PWM outputs are on the RB2/PWM1 and RB3/PWM2 pins. (Slave) Read RCy/PWMx Comparator Each PWM output has a maximum resolution of 10-bits.
PIC17C4X 12.1.3.1 PWM PERIODS The period of the PWM1 output is determined by Timer1 and its period register (PR1). The period of the PWM2 output can be software configured to use either Timer1 or Timer2 as the time-base. When TM2PW2 bit (PW2DCL<5>) is clear, the time-base is determined by TMR1 and PR1. When TM2PW2 is set, the time-base is determined by Timer2 and PR2. Running two different PWM outputs on two different timers allows different PWM periods.
PIC17C4X 12.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR EXTERNAL CLOCK INPUT Timer3 has two modes of operation, depending on the CA1/PR3 bit (TCON2<3>). These modes are: The use of an external clock for the PWM time-base (Timer1 or Timer2) limits the PWM output to a maximum resolution of 8-bits. The PWxDCL<7:6> bits must be kept cleared. Use of any other value will distort the PWM output. All resolutions are supported when internal clock mode is selected. The maximum attainable frequency is also lower.
PIC17C4X 12.2.1 Capture pin RB1/CAP2 is a multiplexed pin. When used as a port pin, Capture2 is not disabled. However, the user can simply disable the Capture2 interrupt by clearing CA2IE. If RB1/CAP2 is used as an output pin, the user can activate a capture by writing to the port pin. This may be useful during development phase to emulate a capture interrupt. ONE CAPTURE AND ONE PERIOD REGISTER MODE In this mode registers PR3H/CA1H and PR3L/CA1L constitute a 16-bit period register.
PIC17C4X 12.2.2 The Capture2 overflow status flag bit is double buffered. The master bit is set if one captured word is already residing in the Capture2 register and another “event” has occurred on the RB1/CA2 pin. The new event will not transfer the TMR3 value to the capture register which protects the previous unread capture value.
PIC17C4X 12.2.3 EXAMPLE 12-2: WRITING TO TMR3 EXTERNAL CLOCK INPUT FOR TIMER3 BSF MOVFP MOVFP BCF When TMR3CS is set, the 16-bit TMR3 increments on the falling edge of clock input TCLK3. The input on the RB5/TCLK3 pin is sampled and synchronized by the internal phase clocks twice every instruction cycle. This causes a delay from the time a falling edge appears on TCLK3 to the time TMR3 is actually incremented. For the external clock input timing requirements, see the Electrical Specification section.
PIC17C4X FIGURE 12-10: TMR1, TMR2, AND TMR3 OPERATION IN TIMER MODE Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 AD15:AD0 ALE MOVF MOVWF MOVF TMR1, W TMR1 TMR1, W Read TMR1 Write TMR1 Read TMR1 Instruction fetched TMR1 04h 05h MOVLB 3 03h 04h BSF TCON2, 0 Stop TMR1 05h NOP BCF TCON2, 0 Start TMR1 06h NOP NOP 07h NOP 08h NOP 00h PR1 TMR1ON WR_TMR1 WR_TCON2 TMR1IF RD_TMR1 TMR1 reads 03h TABLE 12-6: TMR1 read
PIC17C4X NOTES: DS30412C-page 82 1996 Microchip Technology Inc.
PIC17C4X 13.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) MODULE The SPEN (RCSTA<7>) bit has to be set in order to configure RA4 and RA5 as the Serial Communication Interface. The USART module will control the direction of the RA4/RX/DT and RA5/TX/CK pins, depending on the states of the USART configuration bits in the RCSTA and TXSTA registers. The bits that control I/O direction are: The USART module is a serial I/O module.
PIC17C4X FIGURE 13-2: RCSTA REGISTER (ADDRESS: 13h, BANK 0) R/W - 0 R/W - 0 R/W - 0 R/W - 0 SPEN RX9 SREN CREN bit7 U-0 — R- 0 FERR R-0 OERR R-x RX9D bit 0 R = Readable bit W = Writable bit -n = Value at POR reset (x = unknown) bit 7: SPEN: Serial Port Enable bit 1 = Configures RA5/RX/DT and RA4/TX/CK pins as serial port pins 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5: SREN: Single Receive Enable bit This bit enables
PIC17C4X FIGURE 13-3: USART TRANSMIT Sync Master/Slave ÷4 BRG Sync/Async Sync/Async CK/TX Sync/Async TSR ÷ 16 Clock Start 0 1 • • • 7 8 Stop DT Load TXREG 0 1 ••• 7 Data Bus 8 TXEN/ Write to TXREG Bit Count Interrupt TXSTA<0> TXIE FIGURE 13-4: USART RECEIVE OSC BRG Interrupt ÷4 Master/Slave Sync CK Buffer Logic Sync/Async Async/Sync RCIE enable Bit Count ÷ 16 START Detect SPEN RX Buffer Logic Majority Detect Clock Data SREN/ CREN/ Start_Bit RSR MSb LSb Stop 8 7 • • • 1 0 FIF
PIC17C4X 13.1 USART Baud Rate Generator (BRG) Example 13-1 shows the calculation of the baud rate error for the following conditions: The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. Table 13-1 shows the formula for computation of the baud rate for different USART modes.
PIC17C4X TABLE 13-3: BAUD RATE (K) BAUD RATES FOR SYNCHRONOUS MODE FOSC = 33 MHz FOSC = 25 MHz FOSC = 20 MHz FOSC = 16 MHz KBAUD %ERROR SPBRG value (decimal) KBAUD %ERROR SPBRG value (decimal) KBAUD %ERROR SPBRG value (decimal) KBAUD %ERROR SPBRG value (decimal) 0.3 NA — — NA — — NA — — NA — — 1.2 NA — — NA — — NA — — NA — — 2.4 NA — — NA — — NA — — NA — — 9.6 NA — — NA — — NA — — NA — — 19.2 NA — — NA — — 19.53 +1.73 255 19.
PIC17C4X TABLE 13-4: BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODE FOSC = 33 MHz FOSC = 25 MHz FOSC = 20 MHz FOSC = 16 MHz KBAUD %ERROR SPBRG value (decimal) KBAUD %ERROR SPBRG value (decimal) KBAUD %ERROR SPBRG value (decimal) 0.3 NA — — NA — — NA — — NA — — 1.2 NA — — NA — — 1.221 +1.73 255 1.202 +0.16 207 KBAUD %ERROR SPBRG value (decimal) 2.4 2.398 -0.07 214 2.396 0.14 162 2.404 +0.16 129 2.404 +0.16 103 9.6 9.548 -0.54 53 9.53 -0.76 40 9.
PIC17C4X 13.2 USART Asynchronous Mode In this mode, the USART uses standard nonreturn-to-zero (NRZ) format (one start bit, eight or nine data bits, and one stop bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART’s transmitter and receiver are functionally independent but use the same data format and baud rate. The baud rate generator produces a clock x64 of the bit shift rate.
PIC17C4X FIGURE 13-5: ASYNCHRONOUS MASTER TRANSMISSION Write to TXREG Word 1 BRG output (shift clock) TX (RA5/TX/CK pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Word 1 TXIF bit Word 1 Transmit Shift Reg TRMT bit FIGURE 13-6: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG Word 2 Word 1 BRG output (shift clock) TX (RA5/TX/CK pin) Start Bit Bit 0 TXIF bit Bit 1 Word 1 Bit 7/8 Stop Bit Start Bit Bit 0 Word 2 Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg.
PIC17C4X 13.2.2 USART ASYNCHRONOUS RECEIVER Note: The receiver block diagram is shown in Figure 13-4. The data comes in the RA4/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at 16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. Once asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). 13.2.
PIC17C4X 7. Steps to follow when setting up an Asynchronous Reception: 1. 2. 3. 4. 5. 6. Initialize the SPBRG register for the appropriate baud rate. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If interrupts are desired, then set the RCIE bit. If 9-bit reception is desired, then set the RX9 bit. Enable the reception by setting the CREN bit. The RCIF bit will be set when reception completes and an interrupt will be generated if the RCIE bit was set.
PIC17C4X 13.3 USART Synchronous Master Mode In Master Synchronous mode, the data is transmitted in a half-duplex manner; i.e. transmission and reception do not occur at the same time: when transmitting data, the reception is inhibited and vice versa. The synchronous mode is entered by setting the SYNC (TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit is set in order to configure the RA5 and RA4 I/O ports to CK (clock) and DT (data) lines respectively.
PIC17C4X TABLE 13-7: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 TMR3IF TMR2IF TMR1IF Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note1) 16h, Bank 1 PIR RBIF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010 13h, Bank 0 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u 16h, Bank 0 TXREG TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu 17h, Bank 1 PIE RBIE CA2IE CA1IE T
PIC17C4X 13.3.2 Steps to follow when setting up a Synchronous Master Reception: USART SYNCHRONOUS MASTER RECEPTION 1. Once synchronous mode is selected, reception is enabled by setting either the SREN (RCSTA<5>) bit or the CREN (RCSTA<4>) bit. Data is sampled on the RA4/RX/DT pin on the falling edge of the clock. If SREN is set, then only a single word is received. If CREN is set, the reception is continuous until CREN is reset. If both bits are set, then CREN takes precedence.
PIC17C4X TABLE 13-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note1) 16h, Bank 1 PIR RBIF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010 13h, Bank 0 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u 14h, Bank 0 RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu 17h, Bank 1 PIE RBIE CA2IE CA1IE TXIE RCIE 0000 0000 0000 0000
PIC17C4X 13.4 USART Synchronous Slave Mode The synchronous slave mode differs from the master mode in the fact that the shift clock is supplied externally at the RA5/TX/CK pin (instead of being supplied internally in the master mode). This allows the device to transfer or receive data in the SLEEP mode. The slave mode is entered by clearing the CSRC (TXSTA<7>) bit. 13.4.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the sync master and slave modes are identical except in the case of the SLEEP mode.
PIC17C4X TABLE 13-9: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note1) 16h, Bank 1 PIR RBIF CA2IF CA1IF TXIF RCIF 0000 0010 0000 0010 13h, Bank 0 RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u 16h, Bank 0 TXREG TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 xxxx xxxx uuuu uuuu 17h, Bank 1 PIE RBIE CA2IE CA1IE TXIE RCIE 0000 0000 0000 000
PIC17C4X 14.0 SPECIAL FEATURES OF THE CPU The PIC17CXX has a Watchdog Timer which can be shut off only through EPROM bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable.
PIC17C4X 14.1 Configuration Bits The PIC17CXX has up to seven configuration locations (Table 14-1). These locations can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations. Any write to a configuration location, regardless of the data, will program that configuration bit. A TABLWT instruction is required to write to program memory locations. The configuration bits can be read by using the TABLRD instructions.
PIC17C4X FIGURE 14-3: CRYSTAL OPERATION, OVERTONE CRYSTALS (XT OSC CONFIGURATION) C1 OSC1 TABLE 14-3: Osc Type CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Freq C1 C2 32 kHz(1) 100-150 pF 100-150 pF 1 MHz 10-33 pF 10-33 pF 2 MHz 10-33 pF 10-33 pF XT 2 MHz 47-100 pF 47-100 pF 4 MHz 15-68 pF 15-68 pF 8 MHz (2) 15-47 pF 15-47 pF TBD TBD 16 MHz 15-47 pF 15-47 pF 25 MHz 0 (3) 0 (3) 32 MHz (3) Higher capacitance increases the stability of the oscillator but also increases the start-up time and the oscillator
PIC17C4X 14.2.4 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance. Figure 14-5 shows implementation of a parallel resonant oscillator circuit.
PIC17C4X 14.3 Watchdog Timer (WDT) The Watchdog Timer’s function is to recover from software malfunction. The WDT uses an internal free running on-chip RC oscillator for its clock source. This does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction.
PIC17C4X FIGURE 14-8: WATCHDOG TIMER BLOCK DIAGRAM On-chip RC Oscillator(1) Postscaler WDT WDTPS1:WDTPS0 4 - to - 1 MUX WDT Enable Note 1: This oscillator is separate from the external RC oscillator on the OSC1 pin.
PIC17C4X Power-down Mode (SLEEP) 14.4 PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if WDT time-out occurred (and caused wake-up). The Power-down mode is entered by executing a SLEEP instruction. This clears the Watchdog Timer and postscaler (if enabled). The PD bit is cleared and the TO bit is set (in the CPUSTA register). In SLEEP mode, the oscillator driver is turned off. The I/O ports maintain their status (driving high, low, or hi-impedance).
PIC17C4X 14.4.2 MINIMIZING CURRENT CONSUMPTION To minimize current consumption, all I/O pins should be either at VDD, or VSS, with no external circuitry drawing current from the I/O pin. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should be at VDD or VSS. The contributions from on-chip pull-ups on PORTB should also be considered, and disabled when possible. 14.
PIC17C4X 15.0 INSTRUCTION SET SUMMARY The PIC17CXX instruction set consists of 58 instructions. Each instruction is a 16-bit word divided into an OPCODE and one or more operands. The opcode specifies the instruction type, while the operand(s) further specify the operation of the instruction. The PIC17CXX instruction set can be grouped into three types: • byte-oriented • bit-oriented • literal and control operations. These formats are shown in Figure 15-1.
PIC17C4X Table 15-2 lists the instructions recognized by the MPASM assembler. Note 1: Any unused opcode is Reserved. Use of any reserved opcode may cause unexpected operation. Note 2: The shaded instructions are not available in the PIC17C42 All instruction examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. To represent a binary number: 0000 0100b 15.
PIC17C4X 15.2 Q Cycle Activity The 4 Q cycles that make up an instruction cycle (Tcy) can be generalized as: Each instruction cycle (Tcy) is comprised of four Q cycles (Q1-Q4). The Q cycles provide the timing/designation for the Decode, Read, Execute, Write etc., of each instruction cycle. The following diagram shows the relationship of the Q cycles to the instruction cycle.
PIC17C4X TABLE 15-2: PIC17CXX INSTRUCTION SET Mnemonic, Operands Description Cycles 16-bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f,d ADD WREG to f 1 0000 111d ffff ffff OV,C,DC,Z ADDWFC f,d ADD WREG and Carry bit to f 1 0001 000d ffff ffff OV,C,DC,Z ANDWF f,d AND WREG with f 1 0000 101d ffff ffff Z CLRF f,s Clear f, or Clear f and Clear WREG 1 0010 100s ffff ffff None COMF f,d Complement f 1 0001 001d ffff ffff Z 3 CPFSEQ f
PIC17C4X TABLE 15-2: PIC17CXX INSTRUCTION SET (Cont.
PIC17C4X ADDLW ADD Literal to WREG Syntax: [ label ] ADDLW Operands: 0 ≤ k ≤ 255 Operation: (WREG) + k → (WREG) Status Affected: OV, C, DC, Z Encoding: Description: 1011 1 Cycles: 1 Q Cycle Activity: Q1 Example: kkkk kkkk The contents of WREG are added to the 8-bit literal 'k' and the result is placed in WREG.
PIC17C4X ADDWFC ADD WREG and Carry bit to f Syntax: [ label ] ADDWFC Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (WREG) + (f) + C → (dest) Status Affected: OV, C, DC, Z Encoding: 0001 Description: f,d ffff ffff 1 Cycles: Decode Syntax: [ label ] ANDLW Operands: 0 ≤ k ≤ 255 Operation: (WREG) .AND.
PIC17C4X ANDWF AND WREG with f BCF Bit Clear f Syntax: [ label ] ANDWF Syntax: [ label ] BCF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operands: 0 ≤ f ≤ 255 0≤b≤7 Operation: (WREG) .AND. (f) → (dest) Operation: 0 → (f) Status Affected: Z Status Affected: None Encoding: 0000 Description: 101d f,d ffff ffff Encoding: 1000 f,b 1bbb ffff ffff The contents of WREG are AND’ed with register 'f'. If 'd' is 0 the result is stored in WREG.
PIC17C4X BSF Bit Set f BTFSC Bit Test, skip if Clear Syntax: [ label ] BSF Syntax: [ label ] BTFSC f,b Operands: 0 ≤ f ≤ 255 0≤b≤7 Operands: 0 ≤ f ≤ 255 0≤b≤7 Operation: 1 → (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 1000 f,b 0bbb ffff Description: Bit 'b' in register 'f' is set.
PIC17C4X BTFSS Bit Test, skip if Set BTG Bit Toggle f Syntax: [ label ] BTFSS f,b Syntax: [ label ] BTG f,b Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ f ≤ 255 0≤b<7 Operation: skip if (f) = 1 Operation: (f) → (f) Status Affected: None Status Affected: None Encoding: Description: 1001 0bbb ffff ffff If bit 'b' in register 'f' is 1 then the next instruction is skipped.
PIC17C4X CALL Subroutine Call CLRF Clear f Syntax: [ label ] CALL k Syntax: [label] CLRF Operands: 0 ≤ k ≤ 4095 Operands: 0 ≤ f ≤ 255 Operation: PC+ 1→ TOS, k → PC<12:0>, k<12:8> → PCLATH<4:0>; PC<15:13> → PCLATH<7:5> Operation: 00h → f, s ∈ [0,1] 00h → dest Status Affected: None Status Affected: None Encoding: Encoding: Description: 111k kkkk 1 Cycles: 2 Q Cycle Activity: Q1 Q2 HERE Q3 Q4 Execute NOP Execute NOP CALL Before Instruction Address(HERE) After Instruction
PIC17C4X CLRWDT Clear Watchdog Timer COMF Complement f Syntax: [ label ] CLRWDT Syntax: [ label ] COMF Operands: None Operands: Operation: 00h → WDT 0 → WDT postscaler, 1 → TO 1 → PD 0 ≤ f ≤ 255 d ∈ [0,1] Operation: ( f ) → (dest) Status Affected: Z Status Affected: Encoding: TO, PD Encoding: 0000 0000 0000 0100 0001 Words: 1 Words: 1 Cycles: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example: Q3 Q4 Read register ALUSTA Execute NOP REG1 = ? = = = = 0x00 0 1 1 Afte
PIC17C4X CPFSEQ Compare f with WREG, skip if f = WREG CPFSGT Compare f with WREG, skip if f > WREG Syntax: [ label ] CPFSEQ Syntax: [ label ] CPFSGT Operands: 0 ≤ f ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: (f) – (WREG), skip if (f) = (WREG) (unsigned comparison) Operation: (f) − (WREG), skip if (f) > (WREG) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0011 0001 f ffff ffff Description: Compares the contents of data memory location 'f' to the contents o
PIC17C4X CPFSLT Compare f with WREG, skip if f < WREG DAW Decimal Adjust WREG Register Syntax: [label] DAW Syntax: [ label ] CPFSLT Operands: Operands: 0 ≤ f ≤ 255 0 ≤ f ≤ 255 s ∈ [0,1] Operation: (f) – (WREG), skip if (f) < (WREG) (unsigned comparison) Operation: Status Affected: None If [WREG<3:0> >9] .OR.
PIC17C4X DECF Decrement f DECFSZ Decrement f, skip if 0 Syntax: [ label ] DECF f,d Syntax: [ label ] DECFSZ f,d Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (f) – 1 → (dest) Operation: Status Affected: OV, C, DC, Z (f) – 1 → (dest); skip if result = 0 Status Affected: None Encoding: 0000 Description: 1 Cycles: 1 Q Cycle Activity: Q1 ffff Q2 Q3 Q4 Read register 'f' Execute Write to destination Example: DECF CNT, Before Instruction CNT Z ffff
PIC17C4X DCFSNZ Decrement f, skip if not 0 GOTO Unconditional Branch Syntax: Operands: [label] DCFSNZ f,d Syntax: [ label ] 0 ≤ f ≤ 255 d ∈ [0,1] Operands: 0 ≤ k ≤ 8191 Operation: (f) – 1 → (dest); skip if not 0 Operation: k → PC<12:0>; k<12:8> → PCLATH<4:0>, PC<15:13> → PCLATH<7:5> Status Affected: None Status Affected: None Encoding: 0010 011d ffff ffff Encoding: 110k GOTO k kkkk kkkk kkkk Description: The contents of register 'f' are decremented.
PIC17C4X INCF Increment f INCFSZ Increment f, skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (f) + 1 → (dest) Operation: Status Affected: OV, C, DC, Z (f) + 1 → (dest) skip if result = 0 Status Affected: None Encoding: 0001 Description: 010d 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Execute Write to destination INCF CNT, 1 Before Instruction = = = 0xFF 0 ? After Instruction CNT Z C ffff Read regi
PIC17C4X INFSNZ Increment f, skip if not 0 Syntax: [label] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (f) + 1 → (dest), skip if not 0 Status Affected: None Encoding: 0010 Description: INFSNZ f,d 1 Cycles: 1(2) Q Cycle Activity: Q1 Decode ffff ffff Q3 Q4 Read register 'f' Execute Write to destination If skip: Q1 Q2 Q3 Q4 Forced NOP NOP Execute NOP HERE ZERO NZERO Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operation: (WREG) .OR.
PIC17C4X IORWF Inclusive OR WREG with f Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (WREG) .OR. (f) → (dest) Status Affected: Z Encoding: 0000 IORWF 100d f,d ffff ffff Description: Inclusive OR WREG with register 'f'. If 'd' is 0 the result is placed in WREG. If 'd' is 1 the result is placed back in register 'f'.
PIC17C4X MOVFP Move f to p Syntax: [label] Operands: 0 ≤ f ≤ 255 0 ≤ p ≤ 31 Operation: (f) → (p) Status Affected: None Encoding: Description: Cycles: 1 Q Cycle Activity: Q1 Example: pppp ffff ffff Move data from data memory location 'f' to data memory location 'p'. Location 'f' can be anywhere in the 256 word data space (00h to FFh) while 'p' can be 00h to 1Fh. Either ’p' or 'f' can be WREG (a useful special situation).
PIC17C4X MOVLR Move Literal to high nibble in BSR MOVLW Move Literal to WREG Syntax: [ label ] Syntax: [ label ] Operands: Operands: 0 ≤ k ≤ 15 0 ≤ k ≤ 255 Operation: k → (BSR<7:4>) k → (WREG) Operation: Status Affected: None Status Affected: None Encoding: Encoding: 1011 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Decode 101x kkkk uuuu The 4-bit literal 'k' is loaded into the most significant 4-bits of the Bank Select Register (BSR).
PIC17C4X MOVPF Move p to f Syntax: [label] Operands: 0 ≤ f ≤ 255 0 ≤ p ≤ 31 Operation: (p) → (f) Status Affected: Z Encoding: pppp ffff ffff Move data from data memory location 'p' to data memory location 'f'. Location 'f' can be anywhere in the 256 byte data space (00h to FFh) while 'p' can be 00h to 1Fh. Either 'p' or 'f' can be WREG (a useful special situation). MOVPF is particularly useful for transferring a peripheral register (e.g. the timer or an I/O port) to a data memory location.
PIC17C4X MULLW Multiply Literal with WREG MULWF Multiply WREG with f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 255 Operation: (k x WREG) → PRODH:PRODL Operation: (WREG x f) → PRODH:PRODL Status Affected: None Status Affected: None Encoding: MULLW 1011 1100 k kkkk kkkk Encoding: 0011 MULWF 0100 f ffff ffff Description: An unsigned multiplication is carried out between the contents of WREG and the 8-bit literal 'k'.
PIC17C4X NEGW Negate W Syntax: [label] Operands: 0 ≤ F ≤ 255 s ∈ [0,1] Operation: WREG + 1 → (f); WREG + 1 → s Status Affected: OV, C, DC, Z Encoding: 0010 Description: NEGW 110s f,s 1 Cycles: 1 Q Cycle Activity: Q1 Decode ffff ffff Syntax: [ label ] Operands: None Operation: No operation Status Affected: None 0000 NOP 0000 Description: No operation.
PIC17C4X RETFIE Return from Interrupt RETLW Return Literal to WREG Syntax: [ label ] Syntax: [ label ] Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → (PC); 0 → GLINTD; PCLATH is unchanged.
PIC17C4X RETURN Return from Subroutine Syntax: [ label ] Operands: None Operation: TOS → PC; Status Affected: None RLCF Rotate Left f through Carry Syntax: [ label ] RLCF Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: f → d; f<7> → C; C → d<0> Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter.
PIC17C4X RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] RLNCF Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: f → d; f<7> → d<0> Operation: Status Affected: None f → d; f<0> → C; C → d<7> Status Affected: C Encoding: 0010 Description: 001d f,d ffff ffff The contents of register 'f' are rotated one bit to the left. If 'd' is 0 the result is placed in WREG.
PIC17C4X RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operands: 0 ≤ f ≤ 255 s ∈ [0,1] Operation: f → d; f<0> → d<7> Operation: FFh → f; FFh → d Status Affected: None Status Affected: None Encoding: 0010 Description: RRNCF f,d 000d ffff ffff The contents of register 'f' are rotated one bit to the right. If 'd' is 0 the result is placed in WREG. If 'd' is 1 the result is placed back in register 'f'.
PIC17C4X SLEEP Enter SLEEP mode SUBLW Subtract WREG from Literal Syntax: [ label ] SLEEP Syntax: [ label ] SUBLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: 00h → WDT; 0 → WDT postscaler; 1 → TO; 0 → PD Operation: k – (WREG) → (WREG) Status Affected: OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Description: 0000 0000 1 Cycles: 1 Q Cycle Activity: Q1 0010 kkkk kkkk Description: Words: 1 Cycles: 1 Q Cycle Activity: Q1 Decode Example 1: Q2 Q3 Q4 Read liter
PIC17C4X SUBWF Subtract WREG from f Syntax: [ label ] SUBWF f,d Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (f) – (W) → (dest) Status Affected: OV, C, DC, Z Encoding: 0000 Description: 010d ffff Subtract WREG from register 'f' (2’s complement method). If 'd' is 0 the result is stored in WREG. If 'd' is 1 the result is stored back in register 'f'.
PIC17C4X SWAPF Swap f TABLRD Table Read Syntax: [ label ] SWAPF f,d Syntax: [ label ] TABLRD t,i,f Operands: 0 ≤ f ≤ 255 d ∈ [0,1] Operands: Operation: f<3:0> → dest<7:4>; f<7:4> → dest<3:0> 0 ≤ f ≤ 255 i ∈ [0,1] t ∈ [0,1] Operation: Status Affected: None If t = 1, TBLATH → f; If t = 0, TBLATL → f; Prog Mem (TBLPTR) → TBLAT; If i = 1, TBLPTR + 1 → TBLPTR Status Affected: None Encoding: 0001 110d ffff ffff Description: The upper and lower nibbles of register 'f' are exchanged.
PIC17C4X TABLRD Table Read Example1: TABLRD 1, 1, REG ; Before Instruction REG TBLATH TBLATL TBLPTR MEMORY(TBLPTR) = = = = = 0x53 0xAA 0x55 0xA356 0x1234 TABLWT Table Write Syntax: [ label ] TABLWT t,i,f Operands: 0 ≤ f ≤ 255 i ∈ [0,1] t ∈ [0,1] Operation: If t = 0, f → TBLATL; If t = 1, f → TBLATH; TBLAT → Prog Mem (TBLPTR); If i = 1, TBLPTR + 1 → TBLPTR Status Affected: None After Instruction (table write completion) REG TBLATH TBLATL TBLPTR MEMORY(TBLPTR) Example2: TABLRD = = = = =
PIC17C4X TABLWT Table Write Example1: TABLWT 0, 1, REG Before Instruction REG TBLATH TBLATL TBLPTR MEMORY(TBLPTR) = = = = = 0x53 0xAA 0x55 0xA356 0xFFFF TLRD Table Latch Read Syntax: [ label ] TLRD t,f Operands: 0 ≤ f ≤ 255 t ∈ [0,1] Operation: If t = 0, TBLATL → f; If t = 1, TBLATH → f Status Affected: None After Instruction (table write completion) REG TBLATH TBLATL TBLPTR MEMORY(TBLPTR - 1) Example 2: TABLWT = = = = = 0x53 0x53 0x55 0xA357 0x5355 Encoding: 1010 0x53 0xAA 0x55 0xA
PIC17C4X TLWT Table Latch Write TSTFSZ Test f, skip if 0 Syntax: [ label ] TLWT t,f Syntax: [ label ] TSTFSZ f Operands: 0 ≤ f ≤ 255 t ∈ [0,1] Operands: 0 ≤ f ≤ 255 Operation: skip if f = 0 Operation: If t = 0, f → TBLATL; If t = 1, f → TBLATH Status Affected: None Encoding: 0011 0011 ffff ffff Description: If 'f' = 0, the next instruction, fetched during the current instruction execution, is discarded and an NOP is executed making this a two-cycle instruction.
PIC17C4X XORLW Exclusive OR Literal with WREG XORWF Exclusive OR WREG with f Syntax: [ label ] XORWF Syntax: [ label ] XORLW k Operands: Operands: 0 ≤ k ≤ 255 0 ≤ f ≤ 255 d ∈ [0,1] Operation: (WREG) .XOR. k → (WREG) Operation: (WREG) .XOR. (f) → (dest) Status Affected: Z Status Affected: Z Encoding: 1011 0100 kkkk kkkk Description: The contents of WREG are XOR’ed with the 8-bit literal 'k'. The result is placed in WREG.
PIC17C4X NOTES: DS30412C-page 142 1996 Microchip Technology Inc.
PIC17C4X 16.0 DEVELOPMENT SUPPORT 16.
PIC17C4X 16.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC17C4X MPASM allow full symbolic debugging from the Microchip Universal Emulator System (PICMASTER). Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic systems implementation. MPASM has the following features to assist in developing software for specific use applications. 16.14 • Provides translation of Assembler source code to object code for all Microchip microcontrollers. • Macro assembly capability.
DS30412C-page 146 SW006005 SW006005 SW006005 SW007002 SW007002 SW007002 SW007002 PIC16C61 PIC16C62, 62A, 64, 64A PIC16C620, 621, 622 SW006005 SW007002 SW007002 SW007002 SW007002 SW007002 SW007002 SW007002 SW007002 PIC16C71 PIC16C710, 711 PIC16C72 PIC16F83 PIC16C84 PIC16F84 PIC16C923, 924* SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 SW006006 — SW006006 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002 DV005001/ DV005002
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 17.0 PIC17C42 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature ............................................................................................................................... -65˚C to +150˚C Voltage on VDD with respect to VSS ...................................
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 TABLE 17-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES) OSC RC XT EC LF PIC17C42-16 VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: VDD: IDD: IPD: Freq: DS30412C-page 148 4.5V to 5.5V 6 mA max. 5 µA max. at 5.5V (WDT disabled) 4 MHz max. 4.5V to 5.5V 24 mA max. 5 µA max. at 5.5V (WDT disabled) 16 MHz max. 4.5V to 5.5V 24 mA max. 5 µA max. at 5.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 17.1 DC CHARACTERISTICS: DC CHARACTERISTICS Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 17.2 DC CHARACTERISTICS: PIC17C42-16 (Commercial, Industrial) PIC17C42-25 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Operating voltage VDD range as described in Section 17.1 DC CHARACTERISTICS Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Operating voltage VDD range as described in Section 17.1 DC CHARACTERISTICS Parameter No. Sym D080 D081 VOL D082 D083 Characteristic Min Typ† Max Units Output Low Voltage I/O ports (except RA2 and RA3) with TTL buffer – – – – 0.1VDD 0.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +40˚C Operating voltage VDD range as described in Section 17.1 DC CHARACTERISTICS Parameter No. Sym Characteristic Min Typ† Max Units Conditions 12.75 4.75 – 5.0 13.25 5.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 17.3 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase symbols (pp) and their meanings: pp ad Address/Data al ALE cc Capture1 and Capture2 ck CLKOUT or clock dt Data in in INT pin io I/O port mc MCLR oe OE os OSC1 Uppercase symbols and their meanings: S D Driven E Edge F Fall H High I Invalid (Hi-impedance) 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17-1: PARAMETER MEASUREMENT INFORMATION All timings are measure between high and low measurement points as indicated in the figures below. INPUT LEVEL CONDITIONS PORTC, D and E pins VIH = 2.4V VIL = 0.4V Data in valid All other input pins Data in invalid VIH = 0.9VDD VIL = 0.1VDD Data in valid Data in invalid OUTPUT LEVEL CONDITIONS 0.25V VOH = 0.7VDD VDD/2 VOL = 0.3VDD 0.25V 0.25V 0.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 17.4 Timing Diagrams and Specifications FIGURE 17-2: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 OSC2 † † In EC and RC modes only. TABLE 17-2: Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 OSC2 † 13 12 14 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 † In EC and RC modes only. TABLE 17-3: Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer RESET 31 35 Address / Data TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17-5: TIMER0 CLOCK TIMINGS RA1/T0CKI 40 41 42 TABLE 17-5: Parameter No. TIMER0 CLOCK REQUIREMENTS Sym Characteristic 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period * Min No Prescaler With Prescaler No Prescaler With Prescaler Typ† Max Units Conditions 0.5TCY + 20 § 10* 0.5TCY + 20 § 10* TCY + 40 § N — — — — — — — — — — ns ns ns ns ns N = prescale value (1, 2, 4, ...
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17-7: CAPTURE TIMINGS CAP1 and CAP2 (Capture Mode) 50 51 52 TABLE 17-7: Parameter No. 50 51 52 * † CAPTURE REQUIREMENTS Sym Characteristic Min TccL Capture1 and Capture2 input low time TccH Capture1 and Capture2 input high time TccP Capture1 and Capture2 input period 10 * 10 * Typ† Max Units Conditions — — — — ns ns 2 TCY § N — — ns N = prescale value (4 or 16) These parameters are characterized but not tested.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RA5/TX/CK pin 121 121 RA4/RX/DT pin 120 TABLE 17-9: Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17-11: MEMORY INTERFACE WRITE TIMING Q1 Q2 Q3 Q4 Q2 Q1 OSC1 ALE OE 151 WR 150 AD<15:0> 154 data out addr out addr out 152 153 TABLE 17-11: MEMORY INTERFACE WRITE REQUIREMENTS Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 17-12: MEMORY INTERFACE READ TIMING Q1 Q2 Q3 Q4 Q1 Q2 OSC1 166 ALE 164 168 160 OE 165 AD<15:0> Data in Addr out 150 Addr out 162 151 WR 161 163 167 '1' '1' TABLE 17-12: MEMORY INTERFACE READ REQUIREMENTS Parameter No. * † § Sym Characteristic 150 TadV2alL AD<15:0> (address) valid to ALE↓ (address setup time) 151 TalL2adI ALE↓ to address out invalid (address hold time) Min Typ† Max Units Conditions 0.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 18.0 PIC17C42 DC AND AC CHARACTERISTICS The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 4.0 3.5 R = 10k FOSC (MHz) 3.0 2.5 2.0 1.5 Cext = 22 pF, T = 25°C 1.0 0.5 R = 100k 0.0 4.0 4.5 5.0 5.5 6.0 6.5 6.0 6.5 VDD (Volts) FIGURE 18-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 4.0 3.5 R = 3.3k FOSC (MHz) 3.0 2.5 R = 5.1k 2.0 1.5 R = 10k 1.0 Cext = 100 pF, T = 25°C 0.5 R = 100k 0.0 4.0 4.5 5.0 5.5 VDD (Volts) DS30412C-page 164 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 2.0 1.8 1.6 1.4 R = 3.3k FOSC (MHz) 1.2 R = 5.1k 1.0 0.8 R = 10k 0.6 0.4 Cext = 300 pF, T = 25°C 0.2 R = 160k 0.0 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts) TABLE 18-2: RC OSCILLATOR FREQUENCIES Cext Rext 22 pF 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 160k 100 pF 300 pF 1996 Microchip Technology Inc. Average Fosc @ 5V, 25°C 3.33 MHz 353 kHz 3.54 MHz 2.43 MHz 1.30 MHz 129 kHz 1.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD 500 450 400 350 Max @ -40°C gm(µA/V) 300 Typ @ 25°C 250 200 150 Min @ 85°C 100 50 0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 6.0 VDD (Volts) FIGURE 18-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD 20 18 Max @ -40°C 16 14 Typ @ 25°C gm(mA/V) 12 10 8 6 Min @ 85°C 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30412C-page 166 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-7: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C) 100000 IDD (µA) 10000 1000 7.0V 6.5V 6.0V 5.5V 5.0V 4.5V 100 4.0V 10 10k 100k 1M External Clock Frequency (Hz) 10M 100M FIGURE 18-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125°C TO -40°C) 100000 IDD (µA) 10000 7.0V 6.5V 6.0V 5.5V 5.0V 1000 4.5V 4.0V 100 10k 100k 1M 10M 100M External Clock Frequency (Hz) 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-9: TYPICAL IPD vs. VDD WATCHDOG DISABLED 25°C 12 10 IPD(nA) 8 6 4 2 0 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (Volts) IPD(nA) FIGURE 18-10: MAXIMUM IPD vs. VDD WATCHDOG DISABLED 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 Temp. = 85°C Temp. = 70°C Temp. = 0°C 4.0 4.5 5.0 5.5 6.0 Temp. = -40°C 6.5 7.0 VDD (Volts) DS30412C-page 168 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-11: TYPICAL IPD vs. VDD WATCHDOG ENABLED 25°C 30 25 IPD(µA) 20 15 10 5 0 4.0 4.5 5.0 5.5 6.5 6.0 7.0 VDD (Volts) FIGURE 18-12: MAXIMUM IPD vs. VDD WATCHDOG ENABLED 60 50 -40°C 70°C IPD(µA) 40 0°C 85°C 30 20 10 0 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (Volts) 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-13: WDT TIMER TIME-OUT PERIOD vs. VDD 30 25 Max. 85°C WDT Period (ms) 20 Max. 70°C Min. 0°C 15 Typ. 25°C 10 Min. -40°C 5 0 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.5 3.0 VDD (Volts) FIGURE 18-14: IOH vs. VOH, VDD = 3V 0 -2 IOH(mA) -4 -6 Min @ 85°C -8 Typ @ 25°C -10 -12 -14 Max @ -40°C -16 -18 0.0 0.5 1.0 1.5 2.0 VDD (Volts) DS30412C-page 170 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-15: IOH vs. VOH, VDD = 5V IOH(mA) 0 -5 -10 Min @ 85°C -15 -20 Max @ -40°C -25 Typ @ 25°C -30 -35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (Volts) FIGURE 18-16: IOL vs. VOL, VDD = 3V 30 Max. -40°C 25 Typ. 25°C IOL(mA) 20 15 Min. +85°C 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VDD (Volts) 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-17: IOL vs. VOL, VDD = 5V 90 80 70 IOH(mA) Max @ -40°C Typ @ 25°C 60 50 Min @ +85°C 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VDD (Volts) FIGURE 18-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD 2.0 1.8 Max (-40°C to +85°C) 1.6 VTH(Volts) Typ @ 25°C 1.4 1.2 1.0 Min (-40°C to +85°C) 0.8 0.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30412C-page 172 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 18-19: VTH, VIL of I/O PINS (SCHMITT TRIGGER) VS. VDD 5.0 VIH, max (-40°C to +85°C) 4.5 VIH, typ (25°C) 4.0 VIH, min (-40°C to +85°C) VIH, VIL(Volts) 3.5 3.0 VIL, max (-40°C to +85°C) 2.5 VIL, typ (25°C) VIL, min (-40°C to +85°C) 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 18-20: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT AND LF MODES) vs. VDD 3.4 3.2 Typ (25°C) 3.
PIC17C4X NOTES: DS30412C-page 174 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 19.0 PIC17CR42/42A/43/R43/44 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias..................................................................................................................-55 to +125˚C Storage temperature ............................................................................................................................... -65˚C to +150˚C Voltage on VDD with respect to VSS ....................
DS30412C-page 176 PIC17CR42-25 PIC17C42A-25 PIC17C43-25 PIC17CR43-25 PIC17C44-25 PIC17CR42-33 PIC17C42A-33 PIC17C43-33 PIC17CR43-33 PIC17C44-33 JW Devices (Ceramic Windowed Devices) VDD: 2.5V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V VDD: 4.5V to 6.0V IDD: 6 mA max. IDD: 6 mA max. IDD: 6 mA max. IDD: 6 mA max. IDD: 6 mA max. IPD: 5 µA max. at 5.5V IPD: 5 µA max. at 5.5V IPD: 5 µA max. at 5.5V IPD: 5 µA max. at 5.5V IPD: 5 µA max. at 5.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 19.1 DC CHARACTERISTICS: DC CHARACTERISTICS Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 19.2 DC CHARACTERISTICS: DC CHARACTERISTICS Parameter No. Sym D001 D002 VDD VDR D003 VPOR D004 SVDD D010 D011 D014 IDD Characteristic PIC17LC42A/43/LC44 (Commercial, Industrial) PIC17LCR42/43 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Min Supply Voltage 2.5 RAM Data Retention 1.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 19.3 DC CHARACTERISTICS: PIC17CR42/42A/43/R43/44-16 (Commercial, Industrial) PIC17CR42/42A/43/R43/44-25 (Commercial, Industrial) PIC17CR42/42A/43/R43/44-33 (Commercial, Industrial) PIC17LCR42/42A/43/R43/44-08 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Operating voltage VDD range as described in Section 19.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and 0˚C ≤ TA ≤ +70˚C for commercial Operating voltage VDD range as described in Section 19.1 DC CHARACTERISTICS Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C ≤ TA ≤ +40˚C Operating voltage VDD range as described in Section 19.1 DC CHARACTERISTICS Parameter No. Sym Characteristic Min Typ† Max Units Conditions 12.75 4.75 – 5.0 13.25 5.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 19.4 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19-1: PARAMETER MEASUREMENT INFORMATION All timings are measure between high and low measurement points as indicated in the figures below. INPUT LEVEL CONDITIONS PORTC, D and E pins VIH = 2.4V VIL = 0.4V Data in valid All other input pins Data in invalid VIH = 0.9VDD VIL = 0.1VDD Data in valid Data in invalid OUTPUT LEVEL CONDITIONS 0.25V VOH = 0.7VDD VDD/2 VOL = 0.3VDD 0.25V 0.25V 0.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 19.5 Timing Diagrams and Specifications FIGURE 19-2: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 3 1 2 3 4 4 OSC2 † † In EC and RC modes only. TABLE 19-2: Param No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19-3: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 OSC2 † 13 12 18 14 16 19 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 † In EC and RC modes only. TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET 31 35 Address / Data TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19-5: TIMER0 CLOCK TIMINGS RA1/T0CKI 40 41 42 TABLE 19-5: Parameter No. TIMER0 CLOCK REQUIREMENTS Sym Characteristic Min 40 Tt0H T0CKI High Pulse Width No Prescaler 41 Tt0L T0CKI Low Pulse Width With Prescaler No Prescaler With Prescaler 42 Tt0P T0CKI Period * † Typ† Max Units Conditions 0.5TCY + 20 § 10* 0.5TCY + 20 § 10* Greater of: 20 ns or Tcy + 40 § N — — ns — — — — — — — — ns ns ns ns N = prescale value (1, 2, 4, ...
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19-7: CAPTURE TIMINGS CAP1 and CAP2 (Capture Mode) 50 51 52 TABLE 19-7: Parameter No. 50 51 52 * † CAPTURE REQUIREMENTS Sym Characteristic Min Typ† Max Units Conditions TccL Capture1 and Capture2 input low time TccH Capture1 and Capture2 input high time TccP Capture1 and Capture2 input period 10 * 10 * — — — — ns ns 2TCY § N — — ns N = prescale value (4 or 16) These parameters are characterized but not tested.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19-9: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RA5/TX/CK pin 121 121 RA4/RX/DT pin 122 120 TABLE 19-9: SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19-11: MEMORY INTERFACE WRITE TIMING (NOT SUPPORTED IN PIC17LC4X DEVICES) Q1 Q2 Q3 Q4 Q2 Q1 OSC1 ALE OE 151 WR 150 AD<15:0> 154 data out addr out 152 addr out 153 TABLE 19-11: MEMORY INTERFACE WRITE REQUIREMENTS (NOT SUPPORTED IN PIC17LC4X DEVICES) Parameter No.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 19-12: MEMORY INTERFACE READ TIMING (NOT SUPPORTED IN PIC17LC4X DEVICES) Q1 Q2 Q3 Q4 Q1 Q2 OSC1 166 ALE 164 168 160 OE 165 AD<15:0> Data in Addr out Addr out 162 150 WR 161 151 163 167 '1' '1' TABLE 19-12: MEMORY INTERFACE READ REQUIREMENTS (NOT SUPPORTED IN PIC17LC4X DEVICES) Parameter No.
PIC17C4X NOTES: DS30412C-page 192 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 20.0 PIC17CR42/42A/43/R43/44 DC AND AC CHARACTERISTICS The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some graphs or tables the data presented is outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 4.0 3.5 R = 10k FOSC (MHz) 3.0 2.5 2.0 1.5 Cext = 22 pF, T = 25°C 1.0 0.5 R = 100k 0.0 4.0 4.5 5.0 5.5 6.0 6.5 6.0 6.5 VDD (Volts) FIGURE 20-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 4.0 3.5 R = 3.3k FOSC (MHz) 3.0 2.5 R = 5.1k 2.0 1.5 R = 10k 1.0 Cext = 100 pF, T = 25°C 0.5 R = 100k 0.0 4.0 4.5 5.0 5.5 VDD (Volts) DS30412C-page 194 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 2.0 1.8 1.6 1.4 R = 3.3k FOSC (MHz) 1.2 R = 5.1k 1.0 0.8 R = 10k 0.6 0.4 Cext = 300 pF, T = 25°C 0.2 R = 160k 0.0 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts) TABLE 20-2: RC OSCILLATOR FREQUENCIES Cext Rext 22 pF 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 160k 100 pF 300 pF 1996 Microchip Technology Inc. Average Fosc @ 5V, 25°C 3.33 MHz 353 kHz 3.54 MHz 2.43 MHz 1.30 MHz 129 kHz 1.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD 500 450 400 350 Max @ -40°C gm(µA/V) 300 Typ @ 25°C 250 200 150 Min @ 85°C 100 50 0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 6.0 VDD (Volts) FIGURE 20-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD 20 18 Max @ -40°C 16 14 Typ @ 25°C gm(mA/V) 12 10 8 6 Min @ 85°C 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30412C-page 196 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-7: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK 25°C) 100000 IDD (µA) 10000 1000 7.0V 6.5V 6.0V 5.5V 5.0V 4.5V 100 4.0V 10 10k 100k 1M External Clock Frequency (Hz) 10M 100M FIGURE 20-8: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK 125°C TO -40°C) 100000 IDD (µA) 10000 1000 7.0V 6.5V 6.0V 5.5V 5.0V 4.5V 4.0V 100 10k 100k 1M 10M 100M External Clock Frequency (Hz) 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-9: TYPICAL IPD vs. VDD WATCHDOG DISABLED 25°C 12 10 IPD(nA) 8 6 4 2 0 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (Volts) IPD(nA) FIGURE 20-10: MAXIMUM IPD vs. VDD WATCHDOG DISABLED 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 Temp. = 85°C Temp. = 70°C Temp. = 0°C 4.0 4.5 5.0 5.5 6.0 Temp. = -40°C 6.5 7.0 VDD (Volts) DS30412C-page 198 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-11: TYPICAL IPD vs. VDD WATCHDOG ENABLED 25°C 30 25 IPD(µA) 20 15 10 5 0 4.0 4.5 5.0 5.5 6.5 6.0 7.0 VDD (Volts) FIGURE 20-12: MAXIMUM IPD vs. VDD WATCHDOG ENABLED 60 50 -40°C 70°C IPD(µA) 40 0°C 85°C 30 20 10 0 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VDD (Volts) 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-13: WDT TIMER TIME-OUT PERIOD vs. VDD 30 25 Max. 85°C WDT Period (ms) 20 Max. 70°C Min. 0°C 15 Typ. 25°C 10 Min. -40°C 5 0 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.5 3.0 VDD (Volts) FIGURE 20-14: IOH vs. VOH, VDD = 3V 0 -2 IOH(mA) -4 -6 Min @ 85°C -8 Typ @ 25°C -10 -12 -14 Max @ -40°C -16 -18 0.0 0.5 1.0 1.5 2.0 VDD (Volts) DS30412C-page 200 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-15: IOH vs. VOH, VDD = 5V IOH(mA) 0 -5 -10 Min @ 85°C -15 -20 Max @ -40°C -25 Typ @ 25°C -30 -35 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD (Volts) FIGURE 20-16: IOL vs. VOL, VDD = 3V 30 Max. -40°C 25 Typ. 25°C IOL(mA) 20 15 Min. +85°C 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VDD (Volts) 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-17: IOL vs. VOL, VDD = 5V 90 80 70 IOH(mA) Max @ -40°C Typ @ 25°C 60 50 Min @ +85°C 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VDD (Volts) FIGURE 20-18: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS (TTL) VS. VDD 2.0 1.8 Max (-40°C to +85°C) 1.6 VTH(Volts) Typ @ 25°C 1.4 1.2 1.0 Min (-40°C to +85°C) 0.8 0.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30412C-page 202 1996 Microchip Technology Inc.
PIC17C4X Applicable Devices 42 R42 42A 43 R43 44 FIGURE 20-19: VTH, VIL of I/O PINS (SCHMITT TRIGGER) VS. VDD 5.0 VIH, max (-40°C to +85°C) 4.5 VIH, typ (25°C) 4.0 VIH, min (-40°C to +85°C) VIH, VIL(Volts) 3.5 3.0 VIL, max (-40°C to +85°C) 2.5 VIL, typ (25°C) VIL, min (-40°C to +85°C) 2.0 1.5 1.0 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) FIGURE 20-20: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT AND LF MODES) vs. VDD 3.4 3.2 Typ (25°C) 3.
PIC17C4X NOTES: DS30412C-page 204 1996 Microchip Technology Inc.
PIC17C4X 21.0 PACKAGING INFORMATION 21.1 40-Lead Ceramic CERDIP Dual In-line, and CERDIP Dual In-line with Window (600 mil) N E1 E α C Pin No. 1 Indicator Area eA eB D S S1 Base Plane Seating Plane L B1 A1 A3 A A2 e1 B D1 Package Group: Ceramic CERDIP Dual In-Line (CDP) Millimeters Symbol Min Max Inches Notes Min Max α 0° 10° 0° 10° A A1 A2 A3 B B1 C D D1 E E1 e1 eA eB L N S S1 4.318 0.381 3.810 3.810 0.355 1.270 0.203 51.435 48.260 15.240 12.954 2.540 14.986 15.240 3.175 40 1.
PIC17C4X 21.2 40-Lead Plastic Dual In-line (600 mil) N α E1 E C eA eB Pin No. 1 Indicator Area D S S1 Base Plane Seating Plane L B1 A1 A2 A e1 B D1 Package Group: Plastic Dual In-Line (PLA) Millimeters Symbol Min α 0° 10° 0° 10° A A1 A2 B B1 C D D1 E E1 e1 eA eB L N S S1 – 0.381 3.175 0.355 1.270 0.203 51.181 48.260 15.240 13.462 2.489 15.240 15.240 2.921 40 1.270 0.508 5.080 – 4.064 0.559 1.778 0.381 52.197 48.260 15.875 13.970 2.591 15.240 17.272 3.683 40 – – – 0.015 0.125 0.014 0.
PIC17C4X 21.3 44-Lead Plastic Leaded Chip Carrier (Square) D -A- D1 -D- 3 -F- 0.812/0.661 N Pics .032/.026 1.27 .050 2 Sides 0.177 .007 S B D-E S -HA A1 3 D3/E3 D2 0.38 .015 3 -G- 8 F-G S D 0.177 .007 S B A S 2 Sides 9 0.101 Seating .004 Plane -C- 4 E2 E1 E 0.38 .015 F-G S 4 -B- 3 -E- 0.177 .007 S A F-G S 10 0.254 .010 Max 2 0.254 .010 Max 11 -H- 11 0.508 .020 0.508 .020 -H- 2 0.812/0.661 3 .032/.026 1.524 .060 Min 6 6 -C1.651 .065 1.651 .065 R 1.14/0.64 .045/.
PIC17C4X 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) 21.4 4 D D1 5 0.20 M C A-B S D S 0.20 M H A-B S D S 7 0.20 min. 0.05 mm/mm A-B D3 0.13 R min. Index area 6 9 PARTING LINE 0.13/0.30 R α b L C E3 E1 E 1.60 Ref. 0.20 M C A-B S D S 4 TYP 4x 10 e 0.20 M H A-B S B D S 5 7 0.05 mm/mm D A2 A Base Plane Seating Plane A1 Package Group: Plastic MQFP Millimeters Symbol Min Max α 0° A A1 A2 b C D D1 D3 E E1 E3 e L N CP 2.000 0.050 1.950 0.300 0.
PIC17C4X 21.5 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) D D1 1.0ø (0.039ø) Ref. Pin#1 2 11°/13°(4x) Pin#1 2 E 0° Min E1 Θ 11°/13°(4x) Detail B e 3.0ø (0.118ø) Ref. Option 1 (TOP side) Option 2 (TOP side) A1 A2 Detail B A L Detail A R 1 0.08 Min R 0.08/0.20 Base Metal Lead Finish b L c 1.00 Ref. Gage Plane 0.250 c1 L1 1.00 Ref b1 Detail A S 0.
PIC17C4X 21.
PIC17C4X APPENDIX A: MODIFICATIONS APPENDIX B: COMPATIBILITY The following is the list of modifications over the PIC16CXX microcontroller family: To convert code written for PIC16CXX to PIC17CXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. Instruction word length is increased to 16-bit.
PIC17C4X APPENDIX C: WHAT’S NEW APPENDIX D: WHAT’S CHANGED The structure of the document has been made consistent with other data sheets. This ensures that important topics are covered across all PIC16/17 families. Here is an overview of new features. To make software more portable across the different PIC16/17 families, the name of several registers and control bits have been changed. This allows control bits that have the same function, to have the same name (regardless of processor family).
PIC14000 20 o em y or (x ) r wo 2 /I I SP C ,U T) R SA Peripherals g in m am 4K 192 s te by TMR0 I2C/ ADTMR SMBus M 14 11 22 2.7-6.
20 20 20 20 20 20 20 20 PIC16C54A PIC16CR54A PIC16C55 PIC16C56 PIC16C57 PIC16CR57B PIC16C58A PIC16CR58A im um qu — 2K — 2K 1K 512 — 512 RO en 2K — 2K — — — 512 — — — 73 73 72 72 25 24 25 25 25 25 RA D M M at a Fr e 512 yte s) em or TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 ) 12 12 20 20 12 20 12 12 12 12 ns 2.5-6.25 2.0-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.5-6.25 2.0-6.25 2.0-6.25 2.5-6.25 2.5-6.
1996 Microchip Technology Inc. 20 20 20 20 20 PIC16C556 PIC16C558 PIC16C620 PIC16C621 PIC16C622 2K 1K 512 2K 1K 512 128 80 80 128 80 80 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 H 2 2 2 — — — Yes Yes Yes — — — 3 4 4 4 3 3 13 13 13 13 13 13 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.
DS30412C-page 216 20 20 20 20 20 PIC16CR63(1) PIC16C64 PIC16C64A(1) PIC16CR64(1) PIC16C65 Features — 4K 4K — 2K 2K — 4K — 2K 2K 4K — — 2K — — 4K — 2K — — 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 192 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 128 TMR0, TMR1, TMR2 H 2 SPI/I2C, Yes USART 11 11 11 2 SPI/I2C, Yes USART 2 SPI/I2C, Yes USART 8 8 8
(M 14 d r wo Memory M e( ul od R SA T) Peripherals s) ls ne n ha Features 1996 Microchip Technology Inc.
10 10 10 10 PIC16F84(1) PIC16CR84(1) PIC16F83(1) PIC16CR83(1) F — 512 — 1K — — — — — 1K — 1K — — 512 EE (M 36 36 68 68 Da 64 64 64 64 ta Da em 64 ta y or P ( er T TMR0 TMR0 TMR0 TMR0 o M 4 4 4 4 4 Peripherals ) ts ol (V Features 13 13 13 13 13 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.0 18-pin DIP, SOIC 2.0-6.
1996 Microchip Technology Inc. y or em M M T) R SA ) (s le u od ls ne n ha Features 4K 8 PIC16C924 176 TMR0, 1 SPI/I2C TMR1, TMR2 176 TMR0, 1 SPI/I2C TMR1, TMR2 am — — 5 — 4 Com 32 Seg 4 Com 32 Seg ,U 9 8 25 25 27 27 3.0-6.0 3.0-6.0 Yes Yes — — 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE 64-pin SDIP(1), TQFP, 68-pin PLCC, DIE All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
25 25 25 25 25 PIC17C42A PIC17CR42 PIC17C43 PIC17CR43 PIC17C44 im 8K — 4K — 2K u eq 4K — 2K — — RO EP O RO n 454 454 454 232 232 232 M of y en c M io at pe r Pr R y or em (M ) Hz og ra m M Da AM Fr um 2K m em M ) ) TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 TMR0,TMR1, 2 2 TMR2,TMR3 ta ds (W or ( y or ) es by t er M Ti (s le od u er ia S Yes Yes Yes Yes Yes Yes C a
PIC17C4X PIN COMPATIBILITY Devices that have the same package type and VDD, VSS and MCLR pin locations are said to be pin compatible. This allows these different devices to operate in the same socket. Compatible devices may only requires minor software modification to allow proper operation in the application socket (ex., PIC16C56 and PIC16C61 devices). Not all devices in the same package size are pin compatible; for example, the PIC16C62 is compatible with the PIC16C63, but not the PIC16C55.
PIC17C4X NOTES: DS30412C-page 222 1996 Microchip Technology Inc.
PIC17C4X APPENDIX F: ERRATA FOR PIC17C42 SILICON The PIC17C42 devices that you have received have the following anomalies. At present there is no intention for future revisions to the present PIC17C42 silicon. If these cause issues for the application, it is recommended that you select the PIC17C42A device. Note: 1. Design considerations The device must not be operated outside of the specified voltage range.
PIC17C4X NOTES: DS30412C-page 224 1996 Microchip Technology Inc.
PIC17C4X INDEX A ADDLW ............................................................................ 112 ADDWF ............................................................................ 112 ADDWFC ......................................................................... 113 ALU ...................................................................................... 9 ALU STATUS Register (ALUSTA) ..................................... 36 ALUSTA ...............................................................
PIC17C4X Delay From External Clock Edge ....................................... 68 Development Support ...................................................... 143 Development Tools .......................................................... 143 Device Drawings 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) .............. 209 DIGIT BORROW .................................................................. 9 Digit Carry (DC) ..............................................................
PIC17C4X Indirect Addressing Indirect Addressing .................................................... 39 Operation ................................................................... 40 Registers .................................................................... 40 Initialization Conditions For Special Function Registers .... 19 Initializing PORTB .............................................................. 57 Initializing PORTC ..............................................................
PIC17C4X MP-C C Compiler ............................................................. 145 MPSIM Software Simulator ...................................... 143, 145 MULLW ............................................................................ 129 Multiply Examples 16 x 16 Routine .......................................................... 50 16 x 16 Signed Routine .............................................. 51 8 x 8 Routine ..............................................................
PIC17C4X Receive Status and Control Register ................................. 83 Register File Map ............................................................... 33 Registers ALUSTA ............................................................... 27, 36 BRG ........................................................................... 86 BSR ............................................................................ 27 CPUSTA .................................................................... 37 File Map ..
PIC17C4X Timing Diagrams Asynchronous Master Transmission .......................... 90 Asynchronous Reception ........................................... 92 Back to Back Asynchronous Master Transmission .... 90 Interrupt (INT, TMR0 Pins) ......................................... 26 PIC17C42 Capture ................................................... 159 PIC17C42 CLKOUT and I/O .................................... 156 PIC17C42 Memory Interface Read ..........................
PIC17C4X WDT ........................................................................... 99, 103 Clearing the WDT .................................................... 103 Normal Timer ........................................................... 103 Period ....................................................................... 103 Programming Considerations .................................. 103 WDTPS0 ............................................................................ 99 WDTPS1 .....................
PIC17C4X Figure 6-12: Program Counter using The CALL and GOTO Instructions...................................... 41 Figure 6-13: BSR Operation (PIC17C43/R43/44) ........... 42 Figure 7-1: TLWT Instruction Operation........................ 43 Figure 7-2: TABLWT Instruction Operation................... 43 Figure 7-3: TLRD Instruction Operation ........................ 44 Figure 7-4: TABLRD Instruction Operation ................... 44 Figure 7-5: TABLWT Write Timing (External Memory) .........................
PIC17C4X Figure 19-2: Figure 19-3: Figure 19-4: Figure 19-5: Figure 19-6: Figure 19-7: Figure 19-8: Figure 19-9: Figure 19-10: Figure 19-11: Figure 19-12: Figure 20-1: Figure 20-2: Figure 20-3: Figure 20-4: Figure 20-5: Figure 20-6: Figure 20-7: Figure 20-8: Figure 20-9: Figure 20-10: Figure 20-11: Figure 20-12: Figure 20-13: Figure 20-14: Figure 20-15: Figure 20-16: Figure 20-17: Figure 20-18: Figure 20-19: Figure 20-20: External Clock Timing............................... 184 CLKOUT and I/O Timing......
PIC17C4X Table 17-9: Table 17-10: Table 17-11: Table 17-12: Table 18-1: Table 18-2: Table 19-1: Table 19-2: Table 19-3: Table 19-4: Table 19-5: Table 19-6: Table 19-7: Table 19-8: Table 19-9: Table 19-10: Table 19-11: Table 19-12: Table 20-1: Table 20-2: Table E-1: Serial Port Synchronous Transmission Requirements ........................................... 160 Serial Port Synchronous Receive Requirements ........................................... 160 Memory Interface Write Requirements .....
PIC17C4X ON-LINE SUPPORT Microchip provides two methods of on-line support. These are the Microchip BBS and the Microchip World Wide Web (WWW) site. Use Microchip's Bulletin Board Service (BBS) to get current information and help about Microchip products. Microchip provides the BBS communication channel for you to use in extending your technical staff with microcontroller and memory experts.
PIC17C4X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC17C4X PIC17C4X Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. Examples PART NO. – XX X /XX XXX Pattern: Package: Temperature Range: Frequency Range: Device: QTP, SQTP, ROM Code (factory specified) or Special Requirements.
PIC17C4X NOTES: DS30412C-page 238 1996 Microchip Technology Inc.
PIC17C4X NOTES: DS30412C-page 239 1996 Microchip Technology Inc.
Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
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