Information

© 2008 Microchip Technology Inc. DS80171L-page 3
PIC16F87/88
3. Module: Internal RC Oscillator
When any one of the seven INTOSC frequencies
is enabled by the following conditions, it is possible
for the oscillator to overshoot the selected
frequency:
1. A clock switch from INTRC (31 kHz) to an
INTOSC (125 kHz-8 MHz) frequency via the
IRCF bits (OSCCON register).
2. Exit from Sleep mode with the IRCF bits
already configured for an INTOSC frequency.
3. Executing a clock source switch via the SCS
bits (OSCCON register) to the internal RC
oscillator with the IRCF bits already configured
for an INTOSC frequency.
If the selected frequency is 8 MHz, then the
voltage versus frequency specification of the
device may be violated.
Work around
When it is required for the application to run at
8 MHz, it is recommended that the application
does not start executing code at 8 MHz until the
60 ms firmware delay (see issue 2) has
completed. During the 60 ms settling period, the
application can execute code up to 4 MHz. Upon
completion of the 60 ms firmware delay, the 8 MHz
can be selected via the IRCF bits.
Date Codes that pertain to this issue:
All date codes associated with silicon revision B1.
This issue is not found in devices with silicon
revision C2 (Revision ID 0 1000) or later.
4. Module: PORTB Pull-ups
When RBPU = 0 (OPTION_REG register), the
PORTB weak pull-ups will not be disabled by the
input functions of the SSP and/or CCP (Capture
mode) module as indicated by the RB<5:1> I/O
block diagrams in Section 5.0 “I/O Ports”.
Work around
1. If the SSP and/or CCP (Capture mode) module
is enabled, do not enable the PORTB weak
pull-ups and use external pull-up resistors.
OR
2. If the SSP and/or CCP (Capture mode) module
and PORTB pull-ups are enabled, then evalu-
ate the functionality of the SSP (I
2
C™/SPI) or
CCP (Capture mode) module to ensure proper
operation within your application.
Date Codes that pertain to this issue:
All date codes associated with silicon revision B1.
This issue is not found in devices with silicon
revision C2 (Revision ID 0 1000) or later.
5. Module: PORTB
A delay of 1 TOSC will occur if an instruction that
modifies the contents of PORTB simultaneously
occurs when any of the following modules (if
enabled) execute an operation that effects the
signals on their respective PORTB I/O pins.
CCP Module
:
PWM Mode (CCP1CON<3:0> = 11xx)
When CCP1CON<5:4> bits = 10, the PWM output
signal will be delayed by 1 T
OSC when an instruction
to modify the contents of PORTB is executed.
SSP Module
:
SPI Slave Modes (SSPCON<3:0> =
0100 and 0101)
Clock signal is derived from an external source.
Transmission of data (SDO pin) will be delayed by
1T
OSC when an instruction to modify the contents
of PORTB is executed. Reception of data is not
affected.
AUSART Module
:
Synchronous Slave Mode (TXSTA<7> = 0)
Clock signal is derived from an external source.
Transmission of data (TX pin) will be delayed by
1T
OSC when an instruction to modify the contents
of PORTB is executed. Reception of data is not
affected.
Work around
None
Date Codes that pertain to this issue:
All date codes associated with silicon revision B1.
This issue is not found in devices with silicon
revision C2 (Revision ID 0 1000) or later.