Information

PIC16F87/88
DS80171L-page 2 © 2008 Microchip Technology Inc.
2. Module: Internal RC Oscillator IOFS bit
The device data sheet states when an INTOSC
frequency is selected (125, 250, 500 kHz; 1, 2, 4,
8 MHz), the frequency will be stable when the
IOFS bit becomes set (IOFS = 1) at 4 ms. The
following applies for applications relying on time
dependent code.
Under the following conditions, any of the INTOSC
frequencies may not be stable when IOFS
becomes set (IOFS = 1). Devices may vary from
one to the next and may take as long as 60 ms to
become stable.
1. Wake from Sleep, internal RC oscillator is
selected via the SCS bits or Configuration
Word 1 and the IRCF bits are configured for an
INTOSC frequency.
2. POR is executed, internal RC oscillator is
selected via the SCS bits or Configuration
Word 1 and the IRCF bits are configured for an
INTOSC frequency.
3. The INTRC (31.25 kHz) is clocking the device
and a switch to an INTOSC frequency is
executed via modification of the IRCF bits.
4. An alternative oscillator selection is clocking
the device (i.e., HS mode) and a clock switch
to the internal RC oscillator is executed via the
SCS bits with the IRCF bits configured for an
INTOSC frequency.
Work around
Implement the following software delay shown in
Example 1 after an INTOSC frequency has been
enabled and before any frequency dependent appli-
cation code is executed. This routine will delay
application execution approximately 2K-150K T
CY
(instruction cycles are dependent upon the INTOSC
frequency) to ensure a stable INTOSC frequency.
Date Codes that pertain to this issue:
All date codes associated with silicon revision B1.
This issue is not found in devices with silicon
revision C2 (Revision ID 01000) or later.
EXAMPLE 1: DELAY ROUTINE
DlyVarH equ <define address based on application requirements>
DlyVarL equ <define address based on application requirements>
;Load the delay variable DlyVarH with the following value for the selected frequency:
;125kHz 0x0300
;250kHz 0x0600
;500kHz 0x0C00
;1MHz 0x1900
;2MHz 0x3100
;4MHz 0x6200
delay ;insure the correct data memory bank is selected
; for access of data variables
CLRF DlyVarL ;initialize low delay variable
MOVLW 0x62 ;initialize high delay variable
MOVWF DlyVarH
dly_loop
DECFSZ DlyVarL,f ;decrement low variable
GOTO dly_loop
DECFSZ DlyVarH,f ;decrement high variable
GOTO dly_loop
RETURN ;delay done