Information

PIC16F87/88
DS80365A-page 4 © 2008 Microchip Technology Inc.
Change 6. Section 4.7.1
The second paragraph in Section 4.7.1 “RC_RUN
Mode” is changed as shown.
If the system clock does not come from the INTRC
(31.25 kHz) when the SCS bits are changed, and the
IRCF bits in the OSCCON register are configured for a
frequency other than INTRC, the frequency may not be
stable immediately. The IOFS bit (OSCCON<2>) will
be set when the INTOSC or postscaler frequency is
stable, after approximately 100 μs.
Change 7. Table 4-4
The note in Table 4-4 is changed as shown.
TABLE 4-4: CLOCK SWITCHING MODES
Current
System
Clock
SCS Bits <1:0>
Modified to:
Delay
OSTS
Bit
IOFS
Bit
T1RUN
Bit
New
System
Clock
Comments
LP, XT, HS,
T1OSC,
EC, RC
10
(INTRC)
FOSC<2:0> = LP,
XT or HS
8 Clocks of
INTRC
01
(1)
0 INTRC
or
INTOSC
or
INTOSC
Postscaler
The internal RC oscillator
frequency is dependant upon
the IRCF bits.
LP, XT, HS,
INTRC,
EC, RC
01
(T1OSC)
FOSC<2:0> = LP,
XT or HS
8 Clocks of
T1OSC
0 N/A 1 T1OSC T1OSCEN bit must be
enabled.
INTRC
T1OSC
00
FOSC<2:0> = EC
or
FOSC<2:0> = RC
8 Clocks of
EC
or
RC
1 N/A 0 EC
or
RC
INTRC
T1OSC
00
FOSC<2:0> = LP,
XT, HS
1024 Clocks
(OST)
+
8 Clocks of
LP, XT, HS
1 N/A 0 LP, XT, HS During the 1024 clocks,
program execution is clocked
from the secondary oscillator
until the primary oscillator
becomes stable.
LP, XT, HS 00
(Due to Reset)
LP, XT, HS
1024 Clocks
(OST)
1 N/A 0 LP, XT, HS When a Reset occurs, there is
no clock transition sequence.
Instruction execution and/or
peripheral operation is
suspended unless Two-Speed
Start-up mode is enabled, after
which the INTRC will act as the
system clock until the OST
timer has expired.
Note 1: If the new clock source is the INTOSC or INTOSC postscaler, the IOFS bit will be set approximately
100 μs after the clock change.