Information

© 2008 Microchip Technology Inc. DS80365A-page 3
PIC16F87/88
Change 3. Section 4.6.4
Section 4.6.4 “Modifying the IRCF Bits” is
changed as shown.
4.6.4 MODIFYING THE IRCF BITS
The IRCF bits can be modified at any time regardless of
which clock source is currently being used as the system
clock. The internal oscillator allows users to change the
frequency during run time. This is achieved by modifying
the IRCF bits in the OSCCON register. The sequence of
events that occur after the IRCF bits are modified is
dependent upon the initial value of the IRCF bits before
they are modified. If the INTRC (31.25 kHz, IRCF<2:0>
= 000) is running and the IRCF bits are modified to any
other value than ‘000’, the clock source is switched
immediately. The IOFS bit (OSCCON<2>) becomes set
approximately 100 μs later. Code execution continues
while the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit to become set before
continuing. This bit can be monitored to ensure that the
frequency is stable before using the system clock in time
critical applications.
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz, IRCF<2:0>
≠ 000), the clock source is
switched immediately and IOFS remains set.
Change 4. Section 4.6.5
The fourth step of the first of three switching
sequences in Section 4.6.5 “Clock Transition
Sequence” is changed as shown.
4. The IOFS bit is clear to indicate that the clock is
unstable. In approximately 100 μs, the IOFS bit
will become set, indicating INTOSC is stable.
Code execution continues while IOFS is clear.
Time dependent code should wait for IOFS to
become set before continuing.
Change 5. Table 4-3
Table 4-3
is changed as shown, with change bars
indicating new or modified text.
TABLE 4-3: OSCILLATOR DELAY EXAMPLES
Clock Switch
Frequency Oscillator Delay Comments
From To
Sleep/POR
INTRC
T1OSC
31.25 kHz
32.768 kHz
CPU Start-up
(1)
Following a wake-up from Sleep mode or
POR, CPU start-up is invoked to allow the
CPU to become ready for code execution.
INTOSC/
INTOSC
Postscaler
125 kHz-8 MHz
100 μs
(2)
and
CPU Start-up
(1)
INTRC/Sleep EC, RC DC – 20 MHz
INTRC
(31.25 kHz)
EC, RC DC – 20 MHz
Sleep LP, XT, HS 32.768 kHz-20 MHz
1024 Clock Cycles
(OST)
Following a change from INTRC, an OST
of 1024 cycles must occur.
INTRC
(31.25 kHz)
INTOSC/
INTOSC
Postscaler
125 kHz-8 MHz 100 μs
(2)
Refer to Section 4.6.4 “Modifying the
IRCF Bits” for further details.
Note 1: The 5-10 μs start-up delay is based on a 1 MHz system clock.
2: The INTOSC clock source is available immediately and clocks the controller. 100 μs after the INTOSC is
enabled (when IOFS becomes set), the INTOSC frequency is stable and meets specifications.