Datasheet

 2010-2013 Microchip Technology Inc. DS40001430E-page 93
PIC16(L)F720/721
13.0 TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 3-bit prescaler
• Synchronous or asynchronous operation
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
• Selectable Gate Source Polarity
• Gate Toggle Mode
• Gate Single-pulse Mode
• Gate Value Status
• Gate Event Interrupt
Figure 13-1 is a block diagram of the Timer1 module.
FIGURE 13-1: TIMER1 BLOCK DIAGRAM
TMR1H TMR1L
T1SYNC
T1CKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
clock input
2
Set flag bit
TMR1IF on
Overflow
TMR1
(2)
TMR1ON
Note 1: ST buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
T1G
FOSC/4
Internal
Clock
T1CKI
TMR1CS<1:0>
(1)
Synchronize
(3)
det
Sleep input
TMR1GE
0
1
00
01
10
11
From Timer0
From Timer2
T1GPOL
D
Q
CK
Q
0
1
T1GVAL
Single Pulse
Acq. Control
T1GSPM
T1GGO/DONE
T1GSS<1:0>
10
11
00
01
FOSC
Internal
Clock
Reserved
From WDT
Overflow
Match PR2
Overflow
R
D
EN
Q
Q1
RD
T1GCON
Data Bus
det
Interrupt
TMR1GIF
Set
T1CLK
FOSC/2
Internal
Clock
D
EN
Q
T1G_IN
TMR1ON
T1GTM