Datasheet

PIC16(L)F720/721
DS40001430E-page 8  2010-2013 Microchip Technology Inc.
FIGURE 1-1: 20-PIN DEVICE BLOCK DIAGRAM FOR PIC16F720/721
Flash
Program
Memory
8K x 14
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
368 x 8
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
CLKIN
CLKOUT
MCLR
VDD
PORTA
PORTB
PORTC
RA4
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
8
8
Brown-out
Reset
AUSART
Timer0
Timer1
Timer2
RA3
RA1
RA0
8
3
Analog-To-Digital Converter
RB6
RB7
VSS
T0CKI
T1G
T1CKI
Synchronous
SDA
SCL SSSDO
Serial Port
SDI
/
SCK/
TX/CK
RX/DT
Internal
Oscillator
Block
Configuration
Flash
Program
Memory
8K x 14
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
368 x 8
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
MCLR
VDD
PORTB
PORTC
RC1
8
8
Brown-out
Reset
AUSART
Timer0
Timer1
Timer2
8
3
VSS
T0CKI
T1CKI
Synchronous
SDA
SCL SSSDO
Serial Port
SCK/
Configuration
Flash
Program
Memory
(1)
13
Data Bus
8
14
Program
Bus
Instruction Reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
(1)
Direct Addr
7
RAM Addr
9
Addr MUX
Indirect
Addr
FSR Reg
STATUS Reg
MUX
ALU
W Reg
Instruction
Decode &
Control
Timing
Generation
MCLR
VDD
PORTB
PORTC
RA5
8
8
Timer0
Timer1
Timer2
RA2
8
3
RB4
RB5
VSS
T0CKI
T1CKI
Synchronous
SDA
SCL SSSDO
Serial Port
SCK/
Configuration
CCP1
CCP1
AN9
AN0 AN1
AN2 AN3 AN4
AN8
AN10
AN11
LDO
Regulator
AUSART
ICSPCLK
ICSPDAT
ICSP™
AN6AN5
AN7
PMDATL
PMADRL
Self read/
write Flash
memory
Note: PIC16(L)F720 – 2k x 14 Flash, 128 x 8 RAM
PIC16(L)F721 – 4k x 14 Flash, 256 x 8 RAM.