Datasheet

 2010-2013 Microchip Technology Inc. DS40001430E-page 33
PIC16(L)F720/721
PCON 8Eh ---- --qq ---- --uu
(1,5)
---- --uu
T1GCON 8Fh 0000 0x00 uuuu uxuu uuuu uxuu
OSCCON 90h --10 qq-- --10 qq-- --uu qq--
OSCTUNE 91h --00 0000 --uu uuuu --uu uuuu
PR2 92h 1111 1111 1111 1111 uuuu uuuu
SSPADD 93h 0000 0000 0000 0000 uuuu uuuu
SSPMSK 93h 1111 1111 1111 1111 uuuu uuuu
SSPSTAT 94h 0000 0000 0000 0000 uuuu uuuu
WPUB 115h 1111 ---- 1111 ---- uuuu ----
WPUA 95h --11 1111 --11 1111 --uu uuuu
IOCB 116h 0000 ---- 0000 ---- uuuu ----
IOCA 96h --00 0000 --00 0000 --uu uuuu
TXSTA 98h 0000 -010 0000 -010 uuuu -uuu
SPBRG 99h 0000 0000 0000 0000 uuuu uuuu
FVRCON 9Dh q000 --00 q000 --00 uuuu --uu
ADCON1 9Fh -000 ---- -000 ---- -uuu ----
PMDATL 10Ch xxxx xxxx xxxx xxxx uuuu uuuu
PMADRL 10Dh 0000 0000 0000 0000 uuuu uuuu
PMDATH 10Eh --xx xxxx --xx xxxx --uu uuuu
PMADRH 10Fh ---0 0000 ---0 0000 ---u uuuu
ANSELA 185h ---1 -111 ---1 -111 ---u -uuu
ANSELB 186h --11 ---- --11 ---- --uu ----
ANSELC 187h 11-- 1111 11-- 1111 uu-- uuuu
PMCON1 18Ch 1000 -000 1000 -000 1000 -000
TABLE 3-6: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)
Register Address
Power-on Reset/
Brown-out Reset
(1)
MCLR Reset/
WDT Reset
Wake-up from Sleep through
Interrupt/Time-out
Legend: u = unchanged, x = unknown,
- = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 3-8 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.