Datasheet

PIC16(L)F720/721
DS40001430E-page 28  2010-2013 Microchip Technology Inc.
3.4.2 WDT CONTROL
The WDTEN bit is located in the Configuration Word
Register 1. When set, the WDT runs continuously.
The PSA and PS<2:0> bits of the OPTION_REG
register control the WDT period. See Section 12.0
“Timer0 Module” for more information.
FIGURE 3-3: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0
Postscaler
8
PS<2:0>
PSA
TO TMR0
1
10
0
Clock Source
To T 1G
Divide by
512
WDTEN
TMR1GE
T1GSS = 11
WDTEN
WDT Reset
Low-Power
WDT OSC
TABLE 3-3: WDT STATUS
Conditions WDT
WDTEN = 0 Cleared
CLRWDT Command
Exit Sleep + System Clock = INTOSC, EXTCLK