Datasheet
2010-2013 Microchip Technology Inc. DS40001430E-page 17
PIC16(L)F720/721
Bank 1
80h
(
2
)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
81h OPTION_
REG
RABPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h
(
2
)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
83h
(
2
)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
84h
(
2
)
FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
85h
(5)
TRISA — — TRISA5 TRISA4 —
(4)
TRISA2 TRISA1 TRISA0 --11 -111 --11 -111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4
— — — — 1111 ---- 1111 ----
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
88h
— Unimplemented — —
89h
— Unimplemented — —
8Ah
(
1
),(
2
)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh
(
2
)
INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x
8Ch PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh
— Unimplemented — —
8Eh PCON
— — — — — —PORBOR ---- --qq ---- --uu
8Fh T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS1 T1GSS0 0000 0x00 uuuu uxuu
90h OSCCON
— — IRCF1 IRCF0 ICSL ICSS — — --10 qq-- --10 qq--
91h OSCTUNE
— — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 --00 0000 --uu uuuu
92h PR2 Timer2 module Period Register 1111 1111 1111 1111
93h SSPADD ADD<7:0> 0000 0000 0000 0000
93h
(
3
)
SSPMSK MSK<7:0> 1111 1111 1111 1111
94h SSPSTAT SMP CKE D/A
PSR/WUA BF 0000 0000 0000 0000
95h WPUA
— — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111
96h IOCA
— — IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 --00 0000 --00 0000
97h
— Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC
— BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 0000 0000 0000 0000
9Ah
— Unimplemented — —
9Bh
— Unimplemented — —
9Ch
— Unimplemented — —
9Dh FVRCON FVRRDY FVREN TSEN TSRNG
— — ADFVR1 ADFVR0 q000 --00 q000 --00
9Eh
— Unimplemented — —
9Fh ADCON1
— ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
4: This bit is unimplemented and reads as ‘1’.
5: See Register 6-2.