Datasheet

PIC16(L)F720/721
DS40001430E-page 16  2010-2013 Microchip Technology Inc.
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
Bank 0
00h
(
2
)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0 Timer0 module Register xxxx xxxx uuuu uuuu
02h
(
2
)
PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
03h
(
2
)
STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu
04h
(
2
)
FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
05h PORTA
— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx
06h PORTB RB7 RB6 RB5 RB4
— — — — xxxx ---- uuuu ----
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
08h
— Unimplemented — —
09h
— Unimplemented — —
0Ah
(
1
),(
2
)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh
(
2
)
INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 0000 000x 0000 000x
0Ch PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh
— Unimplemented — —
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0
—T1SYNC—TMR1ON0000 -0-0 uuuu -u-u
11h TMR2 Timer2 module Register 0000 0000 0000 0000
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register Low Byte xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register High Byte xxxx xxxx uuuu uuuu
17h CCP1CON
— — DC1 B1 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
19h TXREG AUSART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG AUSART Receive Data Register 0000 0000 0000 0000
1Bh
— Unimplemented — —
1Ch
— Unimplemented — —
1Dh
— Unimplemented — —
1Eh ADRES ADC Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0
— — CHS3 CHS2 CHS1 CHS0 GO/
DONE
ADON --00 0000 --00 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
2: These registers can be addressed from any bank.
3: Accessible only when SSPM<3:0> = 1001.
4: This bit is unimplemented and reads as ‘1’.
5: See Register 6-2.