Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SSOP 20 8-Bit 16 MHz I/O number 17

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 2010-2013 Microchip Technology Inc. DS40001430E-page 135

PIC16(L)F720/721

16.3.2.3 AUSART Synchronous Slave

Reception

The operation of the Synchronous Master and Slave

modes is identical (Section 16.3.1.4 “Synchronous

Master Reception”), with the following exceptions:

• Sleep

• CREN bit is always set, therefore the receiver is

never Idle

• SREN bit, which is a “don’t care” in Slave mode

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCREG register. If the RCIE interrupt enable bit

of the PIE1 register is set, the interrupt generated will

wake the device from Sleep and execute the next

instruction. If the GIE bit is also set, the program will

branch to the interrupt vector.

16.3.2.4 Synchronous Slave Reception Setup

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. If interrupts are desired, set the RCIE bit of the

PIE1 register and the GIE and PEIE bits of the

INTCON register.

3. If 9-bit reception is desired, set the RX9 bit.

4. Verify address detection is disabled by clearing

the ADDEN bit of the RCSTA register.

5. Set the CREN bit to enable reception.

6. The RCIF bit of the PIR1 register will be set

when reception is complete. An interrupt will be

generated if the RCIE bit of the PIE1 register

was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCSTA

8. Retrieve the 8 Least Significant bits from the

receive FIFO by reading the RCREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCSTA

TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

on Page

INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38

PIE1

TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39

PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40

RCREG AUSART Receive Data Register 123

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 126

TRISC TRISC7 TRISC6

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61

TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 125

Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.