Datasheet

PIC16(L)F720/721
DS40001430E-page 124  2010-2013 Microchip Technology Inc.
FIGURE 16-5: ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1bit 0
bit 7/8
bit 0Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 16-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
INTCON GIE PEIE TMR0IE INTE RABIE TMR0IF INTF RABIF 38
PIE1
TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 39
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 40
RCREG AUSART Receive Data Register 123
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 126
SPBRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 127
TRISC TRISC7
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 61
TXSTA
CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 125
Legend: x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for asynchronous reception.