Datasheet

 2011-2013 Microchip Technology Inc. DS40001574C-page 213
PIC16(L)F1938/9
23.3.7 OPERATION IN SLEEP MODE
In Sleep mode, the TMRx register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMRx will continue from its
previous state.
23.3.8 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)”
for additional details.
23.3.9 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
23.3.10 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see
Section 12.1 “Alternate Pin Function” for
more information.
TABLE 23-8: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON
— CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 123
CCPxCON PxM<1:0>
(1)
DCxB<1:0> CCPxM<3:0>
228
CCPTMRS0 C4TSEL<1:0> C3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0>
229
CCPTMRS1
— — — — — — C5TSEL<1:0>
230
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
90
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
91
PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE —CCP2IE
92
PIE3
— CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE —
93
PIR1 TMR1GIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
94
PIR2
OSFIF C2IF C1IF EEIF BCLIF LCDIF —CCP2IF
95
PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF —
96
PRx
Timer2/4/6 Period Register 201*
TxCON — TxOUTPS<3:0> TMRxON TxCKPS<:0>1
203
TMRx Timer2/4/6 Module Register
201
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
125
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
130
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
134
TRISD
(2)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
137
TRISE — — — — —
(3)
TRISE2
(2)
TRISE1
(2)
TRISE0
(2)
140
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Note 1: Applies to ECCP modules only.
2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’.
3: Unimplemented, read as ‘1’.
* Page provides register information.