Datasheet

PIC16LF1904/6/7
DS41569A-page 82 Preliminary  2011 Microchip Technology Inc.
9.1 Independent Clock Source
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1ms. See
Section 22.0 “Electrical Specifications” for the
LFINTOSC tolerances.
9.2 WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word 1. See Ta bl e 9-1.
9.2.1 WDT IS ALWAYS ON
When the WDTE bits of Configuration Word 1 are set to
‘11’, the WDT is always on.
WDT protection is active during Sleep.
9.2.2 WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Word 1 are set to
‘10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
9.2.3 WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Word 1 are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See Table 9-1
for more details.
TABLE 9-1: WDT OPERATING MODES
9.3 Time-Out Period
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.
9.4 Clearing the WDT
The WDT is cleared when any of the following condi-
tions occur:
•Any Reset
• CLRWDT instruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fail event
• WDT is disabled
• Oscillator Start-up TImer (OST) is running
See Table 9-2 for more information.
9.5 Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 6.0 “Oscillator
Module” for more information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO
and PD bits
in the STATUS register are changed to indicate the
event. See Section 3.0 “Memory Organization” and
STATUS register (Register 3-1) for more information.
WDTE<1:0> SWDTEN
Device
Mode
WDT
Mode
11 X XActive
10 X
Awake Active
Sleep Disabled
01
1
X
Active
0 Disabled
00 X X Disabled
TABLE 9-2: WDT CLEARING CONDITIONS
Conditions WDT
WDTE<1:0> = 00
Cleared
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF bits) Unaffected