Datasheet

PIC16LF1904/6/7
DS41569A-page 52 Preliminary  2011 Microchip Technology Inc.
5.3 Low-Power Brown-out Reset
(LPBOR)
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 5-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external V
DD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 5-2.
5.3.1 ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of
Configuration Word 2. When the device is erased, the
LPBOR module defaults to disabled.
5.3.1.1 LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
to be OR’d together with the Reset signal of the BOR
module to provide the generic BOR
signal, which goes
to the PCON register and to the power control block.
5.4 MCLR
The MCLR is an optional external input that can reset
the device. The MCLR
function is controlled by the
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2 (Ta bl e 5-2).
5.4.1 MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR
pin is connected to
V
DD through an internal weak pull-up.
The device has a noise filter in the MCLR
Reset path.
The filter will detect and ignore small pulses.
5.4.2 MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 11.5 “PORTE Regis-
ters” for more information.
5.5 Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO
and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 9.0
“Watchdog Timer” for more information.
5.6 RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Ta ble 5 - 4
for default conditions after a RESET instruction has
occurred.
5.7 Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration Word
2. See Section 5.7 “Stack Overflow/Underflow Reset”
for more information.
5.8 Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
5.9 Power-Up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE
bit of
Configuration Word 1.
5.10 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. Oscillator start-up timer runs to completion (if
required for oscillator source).
3. MCLR
must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Section 6.0 “Oscillator Module” for more informa-
tion.
The Power-up Timer and oscillator start-up timer run
independently of MCLR
Reset. If MCLR is kept low
long enough, the Power-up Timer and oscillator
start-up timer will expire. Upon bringing MCLR
high, the
device will begin execution immediately (see
Figure 5-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
TABLE 5-2: MCLR CONFIGURATION
MCLRE LVP MCLR
00Disabled
10Enabled
x1Enabled
Note: A Reset does not drive the MCLR
pin low.