Datasheet
Table Of Contents
- TABLE 1: 28/40/44-Pin Allocation Table (PIC16LF1904/6/7)
- 1.0 Device Overview
- 2.0 Enhanced Mid-range CPU
- 3.0 Memory Organization
- TABLE 3-1: Device Sizes and Addresses
- FIGURE 3-1: Program Memory Map And Stack For PIC16LF1904
- FIGURE 3-2: Program Memory Map And Stack For PIC16LF1906/7
- TABLE 3-2: Core Registers
- Register 3-1: STATUS: STATUS Register
- FIGURE 3-3: Banked Memory Partitioning
- TABLE 3-3: PIC16LF1904/6/7 Memory Map
- TABLE 3-3: PIC16LF1904/6/7 Memory Map (Continued)
- TABLE 3-3: PIC16LF1904/6/7 Memory Map (Continued)
- TABLE 3-4: Core Function Registers Summary
- TABLE 3-5: Special Function Register Summary
- FIGURE 3-4: Loading Of PC In Different Situations
- FIGURE 3-5: Accessing the Stack Example 1
- FIGURE 3-6: Accessing the Stack Example 2
- FIGURE 3-7: Accessing the Stack Example 3
- FIGURE 3-8: Accessing the Stack Example 4
- FIGURE 3-9: Indirect Addressing
- FIGURE 3-10: Traditional Data Memory Map
- FIGURE 3-11: Linear Data Memory Map
- FIGURE 3-12: Program Flash Memory Map
- 4.0 Device Configuration
- 5.0 Resets
- FIGURE 5-1: Simplified Block Diagram Of On-Chip Reset Circuit
- TABLE 5-1: BOR Operating Modes
- FIGURE 5-2: Brown-Out Situations
- Register 5-1: BORCON: Brown-out Reset Control Register
- TABLE 5-2: MCLR Configuration
- FIGURE 5-3: Reset Start-Up Sequence
- TABLE 5-3: Reset Status Bits and Their Significance
- TABLE 5-4: Reset Condition for Special Registers(2)
- Register 5-2: PCON: Power Control Register
- TABLE 5-5: Summary Of Registers Associated With Resets
- 6.0 Oscillator Module
- FIGURE 6-1: Simplified PIC® MCU Clock Source Block Diagram
- FIGURE 6-2: External Clock (EC) Mode Operation
- FIGURE 6-3: Quartz Crystal Operation (Secondary Oscillator)
- FIGURE 6-4: Internal Oscillator Switch Timing
- Register 6-1: OSCCON: Oscillator Control Register
- Register 6-2: OSCSTAT: Oscillator Status ReGister
- TABLE 6-1: Summary of Registers Associated with Clock Sources
- TABLE 6-2: Summary of cONFIGURATION wORD with Clock Sources
- 7.0 Interrupts
- FIGURE 7-1: Interrupt Logic
- FIGURE 7-2: Interrupt Latency
- FIGURE 7-3: INT Pin Interrupt Timing
- Register 7-1: INTCON: Interrupt Control Register
- Register 7-2: PIE1: Peripheral Interrupt Enable Register 1
- Register 7-3: PIE2: Peripheral Interrupt Enable Register 2
- Register 7-4: PIR1: Peripheral Interrupt Request Register 1
- Register 7-5: PIR2: Peripheral Interrupt Request Register 2
- TABLE 7-1: Summary of Registers Associated with Interrupts
- 8.0 Power-Down Mode (Sleep)
- 9.0 Watchdog Timer
- 10.0 Flash Program Memory Control
- TABLE 10-1: Flash Memory Organization By Device
- FIGURE 10-1: Flash Program Memory Read Flowchart
- FIGURE 10-2: Flash Program Memory Read Cycle Execution
- FIGURE 10-3: Flash Program Memory Unlock Sequence Flowchart
- FIGURE 10-4: Flash Program Memory Erase Flowchart
- FIGURE 10-5: Block WRITES to Flash Program Memory With 32 write latches
- FIGURE 10-6: Flash Program Memory Write Flowchart
- FIGURE 10-7: Flash Program Memory Modify Flowchart
- TABLE 10-2: User ID, Device ID and Configuration Word Access (cfgs = 1)
- FIGURE 10-8: Flash Program Memory Verify Flowchart
- Register 10-1: PMDATL: Program Memory Data Low Byte Register
- Register 10-2: PMDATH: Program Memory Data hIGH bYTE Register
- Register 10-3: PMADRL: Program Memory Address Low Byte Register
- Register 10-4: PMADRH: Program Memory Address hIGH bYTE Register
- Register 10-5: PMCON1: Program Memory Control 1 Register
- Register 10-6: PMCON2: Program Memory Control 2 Register
- TABLE 10-3: Summary of Registers Associated with Flash Program Memory
- TABLE 10-4: Summary of cONFIGURATION wORD with Flash Program Memory
- 11.0 I/O Ports
- TABLE 11-1: Port Availability Per Device
- FIGURE 11-1: Generic I/O Port Operation
- TABLE 11-2: PORTA Output Priority
- Register 11-1: PORTA: PORTA Register
- Register 11-2: TRISA: PORTA Tri-State Register
- Register 11-3: LATA: PORTA Data Latch Register
- Register 11-4: ANSELA: PORTA Analog Select Register
- TABLE 11-3: Summary of Registers Associated with PORTA
- TABLE 11-4: Summary of cONFIGURATION wORD with PORTA
- TABLE 11-5: PORTB Output Priority
- Register 11-5: PORTB: PORTB Register
- Register 11-6: TRISB: PORTB Tri-State Register
- Register 11-7: LATB: PORTB Data Latch Register
- Register 11-8: ANSELB: PORTB Analog Select Register
- Register 11-9: WPUB: WEAK PULL-uP PORTB REGISTER
- TABLE 11-6: Summary of Registers Associated with PORTB
- TABLE 11-7: PORTC Output Priority
- Register 11-10: PORTC: PORTC Register
- Register 11-11: TRISC: PORTC Tri-State Register
- Register 11-12: LATC: PORTC Data Latch Register
- TABLE 11-8: Summary of Registers Associated with PORTC
- TABLE 11-9: PORTD Output Priority
- Register 11-13: PORTD: PORTD Register
- Register 11-14: TRISD: PORTD Tri-State Register
- Register 11-15: LATD: PORTB Data Latch Register
- TABLE 11-10: Summary of Registers Associated with PORTD(1)
- Register 11-16: PORTE: PORTE Register
- Register 11-17: TRISE: PORTE Tri-State Register
- Register 11-18: LATE: PORTE Data Latch Register
- Register 11-19: ANSELE: PORTE Analog Select Register
- Register 11-20: WPUE: WEAK PULL-uP PORTe REGISTER
- TABLE 11-11: Summary of Registers Associated with PORTE
- 12.0 Interrupt-On-Change
- 13.0 Fixed Voltage Reference (FVR)
- 14.0 Temperature Indicator Module
- 15.0 Analog-to-Digital Converter (ADC) Module
- FIGURE 15-1: ADC Block Diagram
- TABLE 15-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies
- FIGURE 15-2: Analog-to-Digital Conversion Tad Cycles
- FIGURE 15-3: 10-Bit A/D Conversion Result Format
- Register 15-1: ADCON0: A/D Control Register 0
- Register 15-2: ADCON1: A/D Control Register 1
- Register 15-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0
- Register 15-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0
- Register 15-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1
- Register 15-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1
- FIGURE 15-4: Analog Input Model
- FIGURE 15-5: ADC Transfer Function
- TABLE 15-2: Summary of Registers Associated with ADC
- 16.0 Timer0 Module
- 17.0 Timer1 Module with Gate Control
- FIGURE 17-1: Timer1 Block Diagram
- TABLE 17-1: Timer1 Enable Selections
- TABLE 17-2: Clock Source Selections
- TABLE 17-3: Timer1 Gate Enable Selections
- TABLE 17-4: Timer1 Gate Sources
- FIGURE 17-2: Timer1 Incrementing Edge
- FIGURE 17-3: Timer1 Gate Enable Mode
- FIGURE 17-4: Timer1 Gate Toggle Mode
- FIGURE 17-5: Timer1 Gate Single-Pulse Mode
- FIGURE 17-6: Timer1 Gate Single-Pulse and Toggle Combined Mode
- Register 17-1: T1CON: Timer1 Control Register
- Register 17-2: T1GCON: Timer1 Gate Control Register
- TABLE 17-5: Summary of Registers Associated with Timer1
- 18.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)
- FIGURE 18-1: EUSART Transmit Block Diagram
- FIGURE 18-2: EUSART Receive Block Diagram
- FIGURE 18-3: Asynchronous Transmission
- FIGURE 18-4: Asynchronous Transmission (Back-to-Back)
- TABLE 18-1: Registers Associated with Asynchronous Transmission
- FIGURE 18-5: Asynchronous Reception
- TABLE 18-2: Registers Associated with Asynchronous Reception
- Register 18-1: TXSTA: Transmit Status AND Control REGISTER
- Register 18-2: RCSTA: Receive Status and Control Register
- Register 18-3: BAUDCON: BAUD RATE CONTROL REGISTER
- TABLE 18-3: Baud Rate Formulas
- TABLE 18-4: Registers Associated with Baud Rate Generator
- TABLE 18-5: BAUD Rates for Asynchronous Modes
- TABLE 18-6: BRG Counter Clock Rates
- FIGURE 18-6: Automatic Baud Rate Calibration
- FIGURE 18-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation
- FIGURE 18-8: Auto-Wake-up Bit (WUE) Timings During Sleep
- FIGURE 18-9: Send Break Character Sequence
- FIGURE 18-10: Synchronous Transmission
- FIGURE 18-11: Synchronous Transmission (Through TXEN)
- TABLE 18-7: Registers Associated with Synchronous Master Transmission
- FIGURE 18-12: Synchronous Reception (Master Mode, SREN)
- TABLE 18-8: Registers Associated with Synchronous Master Reception
- TABLE 18-9: Registers Associated with Synchronous Slave Transmission
- TABLE 18-10: Registers Associated with Synchronous Slave Reception
- 19.0 Liquid Crystal Display (LCD) Driver Module
- FIGURE 19-1: LCD Driver Module Block Diagram
- TABLE 19-1: LCD Segment and Data Registers
- Register 19-1: LCDCON: Liquid Crystal Display (LCD) Control Register
- Register 19-2: LCDPS: LCD Phase Register
- Register 19-3: LCDREF: LCD Reference Voltage Control Register
- Register 19-4: LCDCST: LCD Contrast Control Register
- Register 19-5: LCDSEn: LCD Segment Enable Registers
- Register 19-6: LCDDATAn: LCD Data Registers
- FIGURE 19-2: LCD Clock Generation
- TABLE 19-2: LCD Bias Voltages
- FIGURE 19-3: LCD Bias VOltage Generation Block DIagram
- TABLE 19-3: LCD Internal ladder power modes (1/3 Bias)
- FIGURE 19-4: LCD Internal Reference Ladder power mode switching Diagram – Type A
- FIGURE 19-5: LCD Internal Reference Ladder power mode switching Diagram – Type A Waveform (1/2 MUX, 1/2 Bias Drive)
- FIGURE 19-6: LCD Internal Reference Ladder power mode switching Diagram – Type B Waveform (1/2 MUX, 1/2 Bias Drive)
- Register 19-7: LCDRL: LCD Reference Ladder Control Registers
- FIGURE 19-7: Internal reference and Contrast control Block Diagram
- TABLE 19-4: Common Pin Usage
- TABLE 19-5: Frame Frequency Formulas
- TABLE 19-6: Approximate Frame Frequency (in Hz) Using Fosc @ 8 MHz, Timer1 @ 32.768 kHz or LFINTOSC
- TABLE 19-7: LCD Segment Mapping Worksheet
- FIGURE 19-8: Type-A/Type-B Waveforms in Static Drive
- FIGURE 19-9: Type-A Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 19-10: Type-B Waveforms in 1/2 MUX, 1/2 Bias Drive
- FIGURE 19-11: Type-A Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 19-12: Type-B Waveforms in 1/2 MUX, 1/3 Bias Drive
- FIGURE 19-13: Type-A Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 19-14: Type-B Waveforms in 1/3 MUX, 1/2 Bias Drive
- FIGURE 19-15: Type-A Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 19-16: Type-B Waveforms in 1/3 MUX, 1/3 Bias Drive
- FIGURE 19-17: Type-A Waveforms in 1/4 MUX, 1/3 Bias Drive
- FIGURE 19-18: Type-B Waveforms in 1/4 MUX, 1/3 Bias Drive
- FIGURE 19-19: Waveforms and Interrupt Timing in Quarter-Duty Cycle Drive (Example – Type-B, Non-Static)
- TABLE 19-8: LCD Module Status During Sleep
- FIGURE 19-20: Sleep Entry/Exit when SLPEN = 1
- TABLE 19-9: sUMMARY OF Registers Associated with LCD Operation
- 20.0 In-Circuit Serial Programming™ (ICSP™)
- 21.0 Instruction Set Summary
- 22.0 Electrical Specifications
- FIGURE 22-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C
- FIGURE 22-2: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature
- FIGURE 22-3: POR and POR Rearm with Slow Rising Vdd
- FIGURE 22-4: Load Conditions
- TABLE 22-1: Clock Oscillator Timing Requirements
- TABLE 22-2: Oscillator Parameters
- FIGURE 22-5: CLKOUT and I/O Timing
- TABLE 22-3: CLKOUT and I/O Timing Parameters
- FIGURE 22-6: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing
- FIGURE 22-7: Brown-Out Reset Timing and Characteristics
- FIGURE 22-8: Minimum Pulse width for LPBOR Detection
- TABLE 22-4: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters
- FIGURE 22-9: Timer0 and Timer1 External Clock Timings
- TABLE 22-5: Timer0 and Timer1 External Clock Requirements
- TABLE 22-6: PIC16LF1904/6/7 A/D Converter (ADC) Characteristics:
- TABLE 22-7: PIC16LF1904/6/7 A/D Conversion Requirements
- FIGURE 22-10: PIC16LF1904/6/7 A/D Conversion Timing (Normal Mode)
- FIGURE 22-11: PIC16LF1904/6/7 A/D Conversion Timing (Sleep Mode)
- 23.0 DC and AC Characteristics Graphs and Charts
- 24.0 Development Support
- 25.0 Packaging Information
- Appendix A: Data Sheet Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Reader Response
- Product Identification System
- Worldwide Sales
PIC16LF1904/6/7
DS41569A-page 260 Preliminary 2011 Microchip Technology Inc.
24.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows
®
programming interface supports baseline
(PIC10F, PIC12F5xx, PIC16F5xx), midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC
®
microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
24.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
24.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, K
EELOQ
®
security ICs, CAN,
IrDA
®
, PowerSmart battery management, SEEVAL
®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.