Datasheet

Table Of Contents
2011 Microchip Technology Inc. Preliminary DS41569A-page 163
PIC16LF1904/6/7
FIGURE 18-5: ASYNCHRONOUS RECEPTION
Start
bit
bit 7/8
bit 1bit 0
bit 7/8
bit 0Stop
bit
Start
bit
Start
bit
bit 7/8
Stop
bit
RX/DT pin
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX/DT input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
TABLE 18-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
BAUD1CON
ABDOVF RCIDL SCKP BRG16 WUE ABDEN 166
BAUD2CON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 166
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93
PIE1 TMR1GIE ADIE RCIE
(1)
TXIE
(1)
TMR1IE 94
PIR1
TMR1GIF ADIF RCIF
(1)
TXIF
(1)
TMR1IF 98
RCREG EUSART Receive Register 160*
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 165
SPBRGL EUSART Baud Rate Generator, Low Byte 167*
SPBRGH EUSART Baud Rate Generator, High Byte 167*
TRISC TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 134
TXSTA
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 164
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for asynchronous reception.
* Page provides register information.
Note 1: PIC16LF1904/7 only.