PIC16LF1904/6/7 Data Sheet 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology 2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16LF1904/6/7 28/40/44-Pin 8-Bit Flash Microcontrollers with nanoWatt XLP Technology High-Performance RISC CPU: • C Compiler Optimized Architecture • Only 49 Instructions • Up to 14 Kbytes Self-Write/Read Flash Program Memory Addressing • Up to 256 Bytes Data Memory Addressing • Operating Speed: - DC – 20 MHz clock input @ 3.6V - DC – 16 MHz clock input @ 1.
PIC16LF1904/6/7 Program Memory Flash (words) PIC16LF1904/6/7 Family Types 14 1/1 1 4 29 116 25 11 1/1 1 4 19 72(1) PIC16LF1907 8192 512 36 14 1/1 1 4 29 Note 1: COM3 and SEG15 share a pin, so the total segments are limited to 72 for 28 pin devices.
PIC16LF1904/6/7 FIGURE 2: 28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1906 RE3/MCLR/VPP RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB5/AN13/COM1 RB4/AN11/COM0 28 27 26 25 24 23 22 RA1/AN1/SEG7 RA0/AN0/SEG12 28-Pin UQFN 8 9 10 11 12 13 14 PIC16LF1906 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 3: 40-PIN PDIP PACKAGE DIAGRAM FOR PIC16LF1904/7 40-Pin PDIP 1 40 RB7/ICSPDAT/ICDDAT/SEG13 SEG12/AN0/RA0 2 39 RB6/ICSPCLK/ICDCLK/SEG14 SEG7/AN1/RA1 3 38 RB5/AN13/COM1 COM2/AN2/RA2 4 37 RB4/AN11/COM0 VPP/MCLR/RE3 5 36 SEG4/T0CKI/RA4 6 35 RB2/AN8/SEG25/VLCD2 SEG5/AN4/RA5 SEG21/AN5/RE0 7 34 8 33 RB1/AN10/SEG24/VLCD1 RB0/AN12/INT/SEG0 SEG22/AN6/RE1 9 32 VDD SEG23/AN7/RE2 10 31 VSS VDD 11 30 RD7/SEG20 VSS 12 29 RD6/SEG19 SEG2/CLKIN/RA7 DS4156
PIC16LF1904/6/7 FIGURE 4: 44-PIN TQFP (10X10) PACKAGE DIAGRAM FOR PIC16LF1904/7 44 43 42 41 40 39 38 37 36 35 34 RC6/TX/CK/SEG9 RC5/SEG10 RC4/T1G/SEG11 RD3/SEG16 RD2/SEG28 RD1/SEG27 RD0/COM3 RC3/SEG6 RC2/SEG3 RC1/T1OSI NC 44-Pin TQFP (10x10) 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 5: 40-PIN UQFN (5X5) PACKAGE DIAGRAM FOR PIC16LF1904/7 31 32 34 33 35 36 37 38 39 40 RC6/TX/CK/SEG9 RC5/SEG10 RC4/T1G/SEG11 RD3/SEG16 RD2/SEG28 RD1/SEG27 RD0/COM3 RC3/SEG6 RC2/SEG3 RC1/T1OSI 40-Pin UQFN (5x5) SEG8/DT/RX/RC7 SEG17/RD4 1 2 30 SEG18/RD5 SEG19/RD6 SEG20/RD7 VSS VDD SEG0/INT/AN12/RB0 VLCD1/SEG24/AN10/RB1 VLCD2/SEG25/AN8/RB2 3 29 4 28 27 5 PIC16LF1904/7 6 26 7 25 8 24 23 9 20 19 18 17 16 15 14 13 11 22 21 VLCD3/SEG26/AN9/RB3 COM0/AN1
PIC16LF1904/6/7 Interrupt 19 17 AN0 — — SEG12 — — — 20 18 AN1 — — SEG7 — — — Basic 2 3 Pull-up LCD 27 28 Timers 2 3 A/D RA0 RA1 I/O EUSART 40-Pin UQFN 44-Pin TQFP 40-Pin PDIP(3) 28-Pin UQFN(2) 28/40/44-PIN ALLOCATION TABLE (PIC16LF1904/6/7) 28-Pin PDIP/ SOIC/SSOP(2) TABLE 1: RA2 4 1 4 21 19 AN2 — — COM2 — — — RA3 5 2 5 22 20 AN3/ VREF+ — — SEG15/ COM3(2) — — — — RA4 6 3 6 23 21 — T0CKI — SEG4 — — RA5 7 4 7 24 22 AN4 — — SEG5
PIC16LF1904/6/7 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 19 3.0 Memory Organization ...............................................................................
PIC16LF1904/6/7 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.
PIC16LF1904/6/7 NOTES: DS41569A-page 12 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 1.0 DEVICE OVERVIEW The PIC16LF1904/6/7 are described within this data sheet. They are available in 28, 40 and 44-pin packages. Figure 1-1 shows a block diagram of the PIC16LF1904/6/7 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device.
PIC16LF1904/6/7 FIGURE 1-1: PIC16LF1904/6/7 BLOCK DIAGRAM Program Flash Memory RAM CLKOUT PORTA PORTB Timing Generation CLKIN PORTC CPU INTRC Oscillator Figure 2-1 PORTD MCLR PORTE LCD Temp. Indicator Note 1: DS41569A-page 14 Timer1 Timer0 ADC 10-Bit EUSART FVR See applicable chapters for more information on peripherals. Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 TABLE 1-2: PIC16LF1904/6/7 PINOUT DESCRIPTION Name RA0/AN0/SEG12 RA1/AN1/SEG7 RA2/AN2/COM2 RA3/AN3/VREF+/COM3(2)/ SEG15 RA4/T0CKI/SEG4 RA5/AN4/SEG5 RA6/CLKOUT/SEG1 RA7/CLKIN/SEG2 RB0/AN12/INT/SEG0 RB1(1)/AN10/SEG24/VLCD1 RB2(1)/AN8/SEG25/VLCD2 Function Input Type RA0 TTL AN0 AN SEG12 — RA1 TTL Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. AN LCD Analog output. CMOS General purpose I/O. AN1 AN — A/D Channel 1 input.
PIC16LF1904/6/7 TABLE 1-2: PIC16LF1904/6/7 PINOUT DESCRIPTION (CONTINUED) Name RB3(1)/AN9/SEG26/VLCD3 RB4(1)/AN11/COM0 RB5(1)/AN13/COM1 RB6(1)/ICSPCLK/ICDCLK/ SEG14 (1) RB7 /ICSPDAT/ICDDAT/ SEG13 RC0/T1OSO/T1CKI RC1/T1OSI RC2/SEG3 RC3/SEG6 RC4/T1G/SEG11 RC5/SEG10 RC6/TX/CK/SEG9 RC7/RX/DT/SEG8 Function Input Type RB3 TTL Output Type Description CMOS General purpose I/O. AN9 AN — SEG26 — AN A/D Channel 9 input. LCD Analog output. VLCD3 AN — LCD analog input.
PIC16LF1904/6/7 TABLE 1-2: PIC16LF1904/6/7 PINOUT DESCRIPTION (CONTINUED) Name RD0(2)/COM3 RD1(2)/SEG27 (2) RD2 /SEG28 (2) RD3 /SEG16 RD4(2)/SEG17 (2) RD5 /SEG18 (2) RD6 /SEG19 RD7(2)/SEG20 RE0 (2) /AN5/SEG21 RE1(2)/AN6/SEG22 RE2(2)/AN7/SEG23 RE3/MCLR/VPP Function Input Type RD0 TTL COM3 — RD1 TTL SEG27 — RD2 TTL SEG28 — RD3 TTL SEG16 — RD4 TTL SEG17 — RD5 TTL SEG18 — RD6 TTL SEG19 — RD7 TTL SEG20 — Output Type Description CMOS General purpose I/O.
PIC16LF1904/6/7 NOTES: DS41569A-page 18 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory.
PIC16LF1904/6/7 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer CLKIN CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up
PIC16LF1904/6/7 3.0 MEMORY ORGANIZATION 3.1 These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16LF1904/6/7 family.
PIC16LF1904/6/7 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16LF1904 FIGURE 3-2: PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE On-chip Program Memory PROGRAM MEMORY MAP AND STACK FOR PIC16LF1906/7 PC<14:0> 15 CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 Stack Level 0 Stack Level 1 Stack Level 0 Stack Level 1 Stack Level 15 Stack Level 15 Reset Vector 0000h Reset Vector 0000h Interrupt Vector 0004h 0005h Interrupt Vector 0004h 0005h Page 0 Page 0 07FFh 0800h Page 1 Rollove
PIC16LF1904/6/7 3.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1.
PIC16LF1904/6/7 3.2 3.2.1 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-3): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh).
PIC16LF1904/6/7 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable.
PIC16LF1904/6/7 3.2.2 SPECIAL FUNCTION REGISTER FIGURE 3-3: The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.
2011 Microchip Technology Inc.
PIC16LF1904/6/7 MEMORY MAP (CONTINUED) BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh 40Ch Unimplemented Read as ‘0’ 46Fh 470h Common RAM (Accesses 70h – 7Fh) 47Fh Core Registers (Table 3-2) 48Bh 48Ch 4EFh 4F0h 4FFh BANK 16 Unimplemented Read as ‘0’ Common RAM (Accesses 70h – 7Fh) Preliminary Unimplemented Read as ‘0’ 86Fh 870h 87Fh Common RAM (Accesses 70h – 7Fh) 8EFh 8F0h 8FFh 2011 Microchip Technology Inc.
PIC16LF1904/6/7 TABLE 3-3: PIC16LF1904/6/7 MEMORY MAP (CONTINUED) BANK 15 780h Core Registers (Table 3-2) 78Bh 78Ch Unimplemented Read as ‘0’ 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h LCDCON LCDPS LCDREF LCDCST LCDRL — — LCDSE0 LCDSE1 LCDSE2 LCDSE3 Unimplemented Read as ‘0’ LCDDATA0 LCDDATA1 LCDDATA2(1) LCDDATA3 LCDDATA4 LCDDATA5(1) LCDDATA6 LCDDATA7
PIC16LF1904/6/7 3.2.6 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-4 can be addressed from any Bank.
PIC16LF1904/6/7 TABLE 3-5: Addr Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 00Ch PORTA PORTA Data Latch when written: PORTA pins when read xxxx xxxx uuuu uuuu 00Dh PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 00Eh PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 00Fh PORTD(3) PORTD Data Latch when written: PORTD pins when read xxxx
PIC16LF1904/6/7 TABLE 3-5: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA PORTA Data Latch xxxx xxxx uuuu uuuu 10Dh LATB PORTB Data Latch xxxx xxxx uuuu uuuu 10Eh LATC PORTC Data Latch xxxx xxxx uuuu uuuu 10Eh LATD(3) PORTD Data Latch xxxx xxxx uuuu uuuu 10Eh LATE(3) — — — — — LATE2 LATE1 LATE0 ---- -xxx ---- -uuu 111h to — 115h Unimplemented 116h BORCON
PIC16LF1904/6/7 TABLE 3-5: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 7 38Ch — — 393h Unimplemented 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0000 0000 0000 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0000 0000 0000 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0000 0000 00
PIC16LF1904/6/7 TABLE 3-5: Addr SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Value on POR, BOR Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7A9h LCDDATA9 SEG7 COM3 SEG6 COM3 SEG5 COM3 SEG4 COM3 SEG3 COM3 SEG2 COM3 SEG1 COM3 SEG0 COM3 xxxx xxxx uuuu uuuu 7AAh LCDDATA10 SEG15 COM3 SEG14 COM3 SEG13 COM3 SEG12 COM3 SEG11 COM3 SEG10 COM3 SEG9 COM3 SEG8 COM3 xxxx xxxx uuuu uuuu 7ABh LCDDATA11 SEG23 COM3 SEG22 COM3 SEG20 COM3 SEG19 COM3 SEG18
PIC16LF1904/6/7 3.3 3.3.2 PCL and PCLATH The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-4 shows the five situations for the loading of the PC.
PIC16LF1904/6/7 3.4 3.4.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.
PIC16LF1904/6/7 FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F).
PIC16LF1904/6/7 FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.
PIC16LF1904/6/7 FIGURE 3-9: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2011 Microchip Technology Inc.
PIC16LF1904/6/7 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.
PIC16LF1904/6/7 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
PIC16LF1904/6/7 NOTES: DS41569A-page 42 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers.
PIC16LF1904/6/7 REGISTER 4-1: CONFIGURATION WORD 1 U-1 U-1 R/P-1 — — CLKOUTEN R/P-1 R/P-1 U-1 BOREN<1:0> — bit 13 R/P-1 R/P-1 R/P-1 CP MCLRE PWRTE bit 8 R/P-1 R/P-1 WDTE<1:0> U-1 R/P-1 — R/P-1 FOSC<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13-12 Unimplemented: Read as ‘1’ bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is d
PIC16LF1904/6/7 REGISTER 4-2: CONFIGURATION WORD 2 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 LVP DEBUG LPBOR BORV STVREN — bit 13 bit 8 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be
PIC16LF1904/6/7 4.2 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Word 1. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s.
PIC16LF1904/6/7 4.5 Device ID and Revision ID The memory location 8006h is where the Device ID and Revision ID are stored. The upper nine bits hold the Device ID. The lower five bits hold the Revision ID. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID.
PIC16LF1904/6/7 NOTES: DS41569A-page 48 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 5.0 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. RESETS There are multiple ways to reset this device: • • • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Low-Power Brown-out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event.
PIC16LF1904/6/7 5.1 Power-on Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level.
PIC16LF1904/6/7 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’.
PIC16LF1904/6/7 5.3 Low-Power Brown-out Reset (LPBOR) 5.5 The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2. 5.3.
PIC16LF1904/6/7 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-Up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-Up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2011 Microchip Technology Inc.
PIC16LF1904/6/7 5.11 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON registers are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers.
PIC16LF1904/6/7 5.12 The PCON register bits are shown in Register 5-2.
PIC16LF1904/6/7 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 51 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 55 STATUS — — — TO PD Z DC C 25 WDTCON — — SWDTEN 83 WDTPS<4:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS41569A-page 56 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 6.0 OSCILLATOR MODULE 6.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 6-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external clock circuits.
PIC16LF1904/6/7 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 6-1: Low Power Mode Event Switch (SCS<1:0>) CLKIN EC 2 CLKIN Primary Clock 00 T1CKI/ T1OSO T1OSI Secondary Oscillator (T1OSC) Secondary Clock INTOSC 01 1x Clock Switch MUX Secondary Oscillator Internal Oscillator IRCF<3:0> 4 Start-Up Osc LF-INTOSC (31 kHz) DS41569A-page 58 INTOSC Divide Circuit 16 MHz Primary Osc /1 /2 /4 /8 /16 HF-16 MHz /32 HF-500 kHz /64 HF-250 kHz HF-8 MHz HF-4 MHz HF-2 MHz HF-1 MHz /128 H
PIC16LF1904/6/7 6.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. An example is: oscillator module (EC mode) circuit. Internal clock sources are contained internally within the oscillator module.
PIC16LF1904/6/7 6.2.1.2 6.2.2 Secondary Oscillator The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1CKI/T1OSO and T1OSI device pins. The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 6.3 “Clock Switching” for more information.
PIC16LF1904/6/7 6.2.2.2 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.4 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT) and Watchdog Timer (WDT).
PIC16LF1904/6/7 FIGURE 6-4: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC LFINTOSC (WDT enabled) HFINTOSC LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <3:0> =0 0 System Clock DS41569A-page 62 Preliminary 2011 Microchip Technolo
PIC16LF1904/6/7 6.3 6.3.3 Clock Switching SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.
PIC16LF1904/6/7 6.
PIC16LF1904/6/7 REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q U-0 R-q/q R-0/q U-0 U-0 R-0/0 R-0/q T1OSCR — OSTS HFIOFR — — LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 T1OSCR: Timer1 Oscillator Ready bit If T1OSCEN = 1: 1 = Timer1 oscillator is ready 0 = Timer
PIC16LF1904/6/7 NOTES: DS41569A-page 66 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 7.0 A block diagram of the interrupt logic is shown in Figure 7.1. INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.
PIC16LF1904/6/7 7.1 Operation 7.2 Interrupts are disabled upon any device Reset.
PIC16LF1904/6/7 FIGURE 7-2: INTERRUPT LATENCY CLKIN Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKOUT Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP
PIC16LF1904/6/7 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) PC + 1 — Dummy Cycle Inst (PC) 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) INTF flag is sampled here (every Q1).
PIC16LF1904/6/7 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate interrupt enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction.
PIC16LF1904/6/7 7.6 Interrupt Control Registers Note: 7.6.1 INTCON REGISTER The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 7-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE of the INTCON register.
PIC16LF1904/6/7 7.6.2 PIE1 REGISTER The PIE1 register contains the interrupt enable bits, as shown in Register 7-2. REGISTER 7-2: R/W-0/0 Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16LF1904/6/7 7.6.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 7-3. REGISTER 7-3: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16LF1904/6/7 7.6.4 PIR1 REGISTER The PIR1 register contains the interrupt flag bits, as shown in Register 7-4. REGISTER 7-4: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16LF1904/6/7 7.6.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 7-5. REGISTER 7-5: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16LF1904/6/7 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 INTEDG T0CS T0SE PSA ADIE RCIE TXIE — — — OPTION_REG WPUEN PIE1 TMR1GIE PS<2:0> 141 TMR1IE 73 PIE2 — — — — — LCDIE — — 74 PIR1 TMR1GIF ADIF RCIF TXIF — — — TMR1IF 75 PIR2 — — — — — LCDIF — — 76 Legend: — = unimplemented location, read as ‘0’.
PIC16LF1904/6/7 NOTES: DS41569A-page 78 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. WDT will be cleared but keeps running, if enabled for operation during Sleep. 2. PD bit of the STATUS register is cleared. 3. TO bit of the STATUS register is set. 4. CPU clock is disabled. 5.
PIC16LF1904/6/7 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP. - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared.
PIC16LF1904/6/7 9.0 WATCHDOG TIMER The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events.
PIC16LF1904/6/7 9.1 Independent Clock Source 9.3 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1ms. See Section 22.0 “Electrical Specifications” for the LFINTOSC tolerances. 9.2 The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Word 1. See Table 9-1. WDT IS ALWAYS ON When the WDTE bits of Configuration Word 1 are set to ‘11’, the WDT is always on.
PIC16LF1904/6/7 9.
PIC16LF1904/6/7 NOTES: DS41569A-page 84 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 10.0 10.1.1 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs).
PIC16LF1904/6/7 TABLE 10-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC16LF1904/6/7 10.2.1 Row Erase (words) Write Latches (words) 32 32 FIGURE 10-1: READING THE FLASH PROGRAM MEMORY FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select Program or Configuration Memory (CFGS) To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register.
PIC16LF1904/6/7 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR
PIC16LF1904/6/7 10.2.2 FLASH MEMORY UNLOCK SEQUENCE FIGURE 10-3: The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing.
PIC16LF1904/6/7 10.2.3 ERASING FLASH PROGRAM MEMORY FIGURE 10-4: While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2.
PIC16LF1904/6/7 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2.
PIC16LF1904/6/7 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts.
7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 7 0 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 c0 5 - 0 7 PMDATH 6 0 PMDATL 8 14 10 Program Memory Write Latches 5 14 Write Latch #0 00h PMADRL<4:0> Preliminary 14 CFGS = 0 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config.
PIC16LF1904/6/7 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4.
PIC16LF1904/6/7 10.3 Modifying Flash Program Memory FIGURE 10-7: When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory.
PIC16LF1904/6/7 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2.
PIC16LF1904/6/7 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM.
PIC16LF1904/6/7 10.
PIC16LF1904/6/7 REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1(1) R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 — CFGS LWLO FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6
PIC16LF1904/6/7 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before
PIC16LF1904/6/7 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. Each port has three standard registers for its operation.
PIC16LF1904/6/7 11.1 11.1.2 PORTA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin).
PIC16LF1904/6/7 REGISTER 11-1: PORTA: PORTA REGISTER R/W-x/x R/W-x/x R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RA<7:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes to PORTA are a
PIC16LF1904/6/7 REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 ANSA5: Analog Select between Analog or Digital Function on pins
PIC16LF1904/6/7 11.2 11.2.2 PORTB Registers PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 11-6). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16LF1904/6/7 REGISTER 11-5: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RB<7:0>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Write
PIC16LF1904/6/7 REGISTER 11-8: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: Analog Select between Analog or Digital F
PIC16LF1904/6/7 11.3 11.3.1 PORTC Registers PORTC is an 8-bit wide bidirectional port. The corresponding data direction register is TRISC (Register 11-6). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16LF1904/6/7 REGISTER 11-10: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RC<7:0>: PORTC General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes
PIC16LF1904/6/7 TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 106 Name LATC PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 106 TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 106 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
PIC16LF1904/6/7 11.4 11.4.1 PORTD Registers (PIC16LF1904/7 only) PORTD is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISD (Register 11-14). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC16LF1904/6/7 REGISTER 11-13: PORTD: PORTD REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RD<7:0>: PORTD General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: Writes
PIC16LF1904/6/7 TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1) Name LATD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 112 PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 112 TRISD TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 112 Legend: Note 1: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD. PIC16LF1904/7 only.
PIC16LF1904/6/7 11.5 11.5.1 PORTE Registers RE3 is input only, and also functions as MCLR. The MCLR feature can be disabled via a configuration fuse. RE3 also supplies the programming voltage. The TRIS bit for RE3 (TRISE3) always reads ‘1’. PORTE FUNCTIONS AND OUTPUT PRIORITIES No output priorities, RE3 is an input only pin.
PIC16LF1904/6/7 REGISTER 11-18: LATE: PORTE DATA LATCH REGISTER U-0 U-0 — U-0 — — U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u (2) (2) LATE0(2) LATE2 LATE1 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LATE<2:0>: PORTE Output Latch Value bits(1) Note 1: 2: Writes to POR
PIC16LF1904/6/7 REGISTER 11-20: WPUE: WEAK PULL-UP PORTE REGISTER U-0 U-0 U-0 U-0 R/W-1/1 U-0 U-0 U-0 — — — — WPUE3 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 WPUE3: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 2-0 Unimplemented:
PIC16LF1904/6/7 12.0 INTERRUPT-ON-CHANGE 12.3 The PORTB pins can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt.
PIC16LF1904/6/7 12.
PIC16LF1904/6/7 TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 107 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 118 Name IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 118 IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
PIC16LF1904/6/7 NOTES: DS41569A-page 120 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 13.0 FIXED VOLTAGE REFERENCE (FVR) 13.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x or 2x, to produce the two possible voltage levels. The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with 1.024V or 2.048V selectable output levels.
PIC16LF1904/6/7 13.
PIC16LF1904/6/7 14.0 TEMPERATURE INDICATOR MODULE FIGURE 14-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.
PIC16LF1904/6/7 NOTES: DS41569A-page 124 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 15.0 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC16LF1904/6/7 15.1 15.1.4 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 15.1.1 The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.
PIC16LF1904/6/7 TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 (2) 200 ns (2) 250 ns (2) FOSC/8 001 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 010 FOSC/64 FRC FOSC/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 1.0 s 2.0 s 4.0 s 16.0 s(3) 1.6 s 2.
PIC16LF1904/6/7 15.1.5 INTERRUPTS 15.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.
PIC16LF1904/6/7 15.2 15.2.1 15.2.4 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 15.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 15.2.5 “A/D Conversion Procedure”.
PIC16LF1904/6/7 15.2.5 A/D CONVERSION PROCEDURE EXAMPLE 15-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16LF1904/6/7 15.2.6 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC16LF1904/6/7 REGISTER 15-2: R/W-0/0 ADCON1: A/D CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 U-0 — — R/W-0/0 R/W-0/0 ADPREF<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: A/D Result Format Select bit 1 = Right justified.
PIC16LF1904/6/7 REGISTER 15-3: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 15-4: R/W-x/u ADR
PIC16LF1904/6/7 REGISTER 15-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use.
PIC16LF1904/6/7 15.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 15-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 15-4.
PIC16LF1904/6/7 FIGURE 15-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.
PIC16LF1904/6/7 TABLE 15-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 131 ADCON1 ADFM ADCS2 ADCS1 ADCS0 — — ADPREF1 ADPREF0 132 ADRESH A/D Result Register High ADRESL A/D Result Register Low 133, 134 133, 134 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 104 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 107 INTCON GIE PEIE TMR0IE INTE I
PIC16LF1904/6/7 NOTES: DS41569A-page 138 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 16.0 16.1.2 TIMER0 MODULE 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’ .
PIC16LF1904/6/7 16.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register.
PIC16LF1904/6/7 REGISTER 16-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled
PIC16LF1904/6/7 NOTES: DS41569A-page 142 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 17.0 • Gate Value Status • Gate Event Interrupt TIMER1 MODULE WITH GATE CONTROL Figure 17-1 is a block diagram of the Timer1 module.
PIC16LF1904/6/7 17.1 Timer1 Operation 17.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 17-2 displays the clock source selections. 17.2.1 When used with an internal clock source, the module is a timer and increments on every instruction cycle.
PIC16LF1904/6/7 17.3 17.5.1 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 17.
PIC16LF1904/6/7 17.6.2 TIMER1 GATE SOURCE SELECTION 17.6.4 The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 17-4: TIMER1 GATE SOURCES T1GSS Timer1 Gate Source 00 Timer1 Gate Pin 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 17.6.2.
PIC16LF1904/6/7 17.7 Timer1 Interrupt 17.8 The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC16LF1904/6/7 FIGURE 17-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL Timer1 N FIGURE 17-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL Timer1 DS41569A-page 148 N N+1 N+2 N+3 N+4 Preliminary N+5 N+6 N+7 N+8 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 17-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF N N+1 Set by hardware on falling edge of T1GVAL Cleared by software 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 17-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL Timer1 TMR1GIF DS41569A-page 150 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of T1GVAL Preliminary N+4 Cleared by software 2011 Microchip Technology Inc.
PIC16LF1904/6/7 17.9 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 17-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC16LF1904/6/7 17.10 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), shown in Register 17-2, is used to control Timer1 gate.
PIC16LF1904/6/7 TABLE 17-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 72 TMR1GIE ADIE RCIE TXIE — — — TMR1IE 73 PIR1 TMR1GIF ADIF RCIF TXIF — — — TMR1IF 75 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 147* TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 147* PIE1 TRISC
PIC16LF1904/6/7 NOTES: DS41569A-page 154 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 18.0 The EUSART module includes the following capabilities: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) • • • • • • • • • • The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC16LF1904/6/7 FIGURE 18-2: EUSART RECEIVE BLOCK DIAGRAM CREN RX/DT pin Baud Rate Generator Data Recovery FOSC SPBRGH SPBRGL x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) ••• 7 1 LSb 0 START RX9 ÷n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receiv
PIC16LF1904/6/7 18.1 18.1.1.2 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16LF1904/6/7 18.1.1.5 TSR Status 18.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. 1. 2. 3. 4.
PIC16LF1904/6/7 FIGURE 18-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 BRG Output (Shift Clock) TX/CK pin Word 2 Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions.
PIC16LF1904/6/7 18.1.2 EUSART ASYNCHRONOUS RECEIVER 18.1.2.2 The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 18-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16LF1904/6/7 18.1.2.4 Receive Interrupts 18.1.2.7 The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software.
PIC16LF1904/6/7 18.1.2.9 Asynchronous Reception Set-up: 1. 18.1.2.10 Initialize the SPBRGH:SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 18.3 “EUSART Baud Rate Generator (BRG)”). 2. Set the RX/DT and TX/CK TRIS controls to ‘1’. 3. Enable the serial port by setting the SPEN bit and the RX/DT pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 4.
PIC16LF1904/6/7 FIGURE 18-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin bit 1 Start bit bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg bit 0 Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG RCIDL bit 7/8 Stop bit Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RX/DT input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC16LF1904/6/7 18.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 18-1: The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output.
PIC16LF1904/6/7 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX
PIC16LF1904/6/7 REGISTER 18-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-ba
PIC16LF1904/6/7 18.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH:SPBRGL register pair determines the period of the free running baud rate timer.
PIC16LF1904/6/7 TABLE 18-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 166 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 166 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 165 RCSTA SPBRGL EUSART Baud Rate Generator, Low Byte SPBRGH TXSTA Legend: * 167* EUSART Baud Rate Generator, High Byte CSRC TX9 TXEN SYNC SENDB BRGH 167* TRMT TX9D 164
PIC16LF1904/6/7 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 16.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.
PIC16LF1904/6/7 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC16LF1904/6/7 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200.1 0.00 0.01 13332 3332 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.
PIC16LF1904/6/7 18.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC16LF1904/6/7 18.3.2 AUTO-BAUD OVERFLOW 18.3.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRGL register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX/DT pin.
PIC16LF1904/6/7 FIGURE 18-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC16LF1904/6/7 18.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC16LF1904/6/7 18.4 18.4.1.2 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16LF1904/6/7 18.4.1.5 1. 2. 3. Synchronous Master Transmission Set-up: 4. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 18.3 “EUSART Baud Rate Generator (BRG)”). Set the RX/DT and TX/CK TRIS controls to ‘1’. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RX/DT and TX/CK I/O pins. 5. 6. 7. FIGURE 18-10: 8. 9.
PIC16LF1904/6/7 TABLE 18-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 166 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 166 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 TXIE(1) INTCON PIE1 TMR1GIE ADIE RCIE(1) — — — TMR1IE 94 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — — TMR1IF 98 SPEN RX9 SREN CREN ADDEN FERR OE
PIC16LF1904/6/7 18.4.1.6 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16LF1904/6/7 FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16LF1904/6/7 18.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC16LF1904/6/7 TABLE 18-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 166 BAUD2CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 166 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 93 TXIE(1) INTCON PIE1 TMR1GIE ADIE RCIE(1) — — — TMR1IE 94 PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — — TMR1IF 98 SPEN RX9 SREN CREN ADDEN FERR OER
PIC16LF1904/6/7 18.4.2.3 EUSART Synchronous Slave Reception 18.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 18.4.1.6 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16LF1904/6/7 NOTES: DS41569A-page 184 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 19.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE 19.1 The module contains the following registers: The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16LF1904/6/7 device, the module drives the panels of up to four commons and up to 116 total segments. The LCD module also provides control of the LCD pixel data.
PIC16LF1904/6/7 TABLE 19-1: LCD SEGMENT AND DATA REGISTERS # of LCD Registers Device Segment Enable Data 4 16 PIC16LF1904/6/7 The LCDCON register (Register 19-1) controls the operation of the LCD driver module. The LCDPS register (Register 19-2) configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B. The LCDSEn registers (Register 19-5) configure the functions of the port pins.
PIC16LF1904/6/7 REGISTER 19-1: LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER R/W-0/0 R/W-0/0 R/C-0/0 U-0 LCDEN SLPEN WERR — R/W-0/0 R/W-0/0 R/W-1/1 CS<1:0> R/W-1/1 LMUX<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 LCDEN: LCD Driver Enable bit 1 = LCD driver module i
PIC16LF1904/6/7 REGISTER 19-2: LCDPS: LCD PHASE REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 WFT BIASMD LCDA WA R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 LP<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 WFT: Waveform Type bit 1 = Type-B phase changes on each frame boundary 0 = Type-A phase cha
PIC16LF1904/6/7 REGISTER 19-3: LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 LCDIRE — LCDIRI — VLCD3PE VLCD2PE VLCD1PE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7 LCDIRE: LCD Internal Reference Enable bit 1 = Internal LCD
PIC16LF1904/6/7 REGISTER 19-4: LCDCST: LCD CONTRAST CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0/0 R/W-0/0 R/W-0/0 LCDCST<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared C = Only clearable bit bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 LCDCST<2:0>: LCD Contrast Control bits Selects the resistanc
PIC16LF1904/6/7 REGISTER 19-5: LCDSEn: LCD SEGMENT ENABLE REGISTERS R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SEn SEn SEn SEn SEn SEn SEn SEn bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of th
PIC16LF1904/6/7 19.2 Using bits CS<1:0> of the LCDCON register can select any of these clock sources. LCD Clock Source Selection The LCD module has 3 possible clock sources: 19.2.1 • FOSC/256 • T1OSC • LFINTOSC The first clock source is the system clock divided by 256 (FOSC/256). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable.
PIC16LF1904/6/7 19.
PIC16LF1904/6/7 19.4 19.4.2 LCD Bias Internal Reference Ladder The internal reference ladder can be used to divide the LCD bias voltage two or three equally spaced voltages that will be supplied to the LCD segment pins. To create this, the reference ladder consists of three matched resistors. Refer to Figure 19-3. POWER MODES The internal reference ladder may be operated in one of three power modes. This allows the user to trade off LCD contrast for power in the specific application.
PIC16LF1904/6/7 19.4.3 AUTOMATIC POWER MODE SWITCHING The LCDRL register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time when the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT<2:0> bits select how long, if any, that the ‘A’ Power mode is active. Refer to Figure 19-4.
LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE) Single Segment Time Single Segment Time 32 kHz Clock Ladder Power Control ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F Segment Clock Segment Data Power Mode Power Mode A LRLAT<2:0> = 011 Power Mode B Power Mode A Power Mode B LRLAT<2:0> = 011 Preliminary V2 V1 COM0-SEG0 V0 -V1 -V2 PIC16LF1904/6/7 DS41569A-page 196 FIGURE 19-5: 201
2011 Microchip Technology Inc.
PIC16LF1904/6/7 REGISTER 19-7: R/W-0/0 LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS R/W-0/0 LRLAP<1:0> R/W-0/0 R/W-0/0 LRLBP<1:0> U-0 R/W-0/0 — R/W-0/0 R/W-0/0 LRLAT<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 LRLAP<1:0>: LCD Reference Ladder A Time Power Control bits During Time interval A (Refe
PIC16LF1904/6/7 19.4.4 CONTRAST CONTROL The LCD contrast control circuit consists of a seven-tap resistor ladder, controlled by the LCDCST bits. Refer to Figure 19-7. FIGURE 19-7: The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST = 111. Whenever the LCD module is inactive (LCDA = 0), the contrast control ladder will be turned off (open).
PIC16LF1904/6/7 19.5 TABLE 19-5: LCD Multiplex Types The LCD driver module can be configured into one of four multiplex types: • • • • Multiplex Frame Frequency(2) = Static Clock source(1)/(4 x (LCD Prescaler) x 32 x 1)) 1/2 Clock source(1)/(2 x (LCD Prescaler) x 32 x 2)) 1/3 Clock source(1)/(1 x (LCD Prescaler) x 32 x 3)) 1/4 Clock source(1)/(1 x (LCD Prescaler) x 32 x 4)) Note 1: Clock source is FOSC/256, T1OSC or LFINTOSC.
PIC16LF1904/6/7 TABLE 19-7: LCD Function LCD SEGMENT MAPPING WORKSHEET COM0 LCDDATAx Address COM1 LCD Segment LCDDATAx Address COM2 LCD Segment LCDDATAx Address COM3 LCD Segment LCDDATAx Address SEG0 LCDDATA0, 0 LCDDATA3, 0 LCDDATA6, 0 LCDDATA9, 0 SEG1 LCDDATA0, 1 LCDDATA3, 1 LCDDATA6, 1 LCDDATA9, 1 SEG2 LCDDATA0, 2 LCDDATA3, 2 LCDDATA6, 2 LCDDATA9, 2 SEG3 LCDDATA0, 3 LCDDATA3, 3 LCDDATA6, 3 LCDDATA9, 3 SEG4 LCDDATA0, 4 LCDDATA3, 4 LCDDATA6, 4 LCDDATA9, 4 SEG5 LCDDATA0, 5
PIC16LF1904/6/7 19.9 LCD Waveform Generation LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and it can take only one of the two RMS values.
PIC16LF1904/6/7 FIGURE 19-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 pin COM1 V1 V0 V2 COM1 pin COM0 V1 V0 V2 V1 SEG0 pin V0 V2 V1 SEG1 pin SEG1 V2 SEG0 SEG2 SEG3 V0 V1 V0 COM0-SEG0 segment voltage (active) -V1 -V2 V2 V1 V0 COM0-SEG1 segment voltage (inactive) -V1 1 Frame -V2 1 Segment Time Note: 1 Frame = 2 single segment times. 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 19-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM1 V1 COM0 pin V0 COM0 V2 COM1 pin V1 V0 V2 SEG0 pin V1 SEG1 SEG0 SEG3 SEG2 V0 V2 SEG1 pin V1 V0 V2 V1 V0 COM0-SEG0 segment voltage (active) -V1 -V2 V2 V1 V0 COM0-SEG1 segment voltage (inactive) -V1 2 Frames -V2 1 Segment Time Note: 1 Frame = 2 single segment times. DS41569A-page 204 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 19-11: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 COM1 V2 COM0 pin V1 V0 V3 COM0 V2 COM1 pin V1 V0 V3 V2 SEG0 pin V1 V0 SEG1 SEG0 SEG2 SEG3 V3 V2 SEG1 pin V1 V0 V3 V2 V1 V0 COM0-SEG0 segment voltage (active) -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 segment voltage (inactive) -V1 1 Frame -V2 -V3 1 Segment Time Note: 1 Frame = 2 single segment times. 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 19-12: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 COM1 V2 COM0 pin V1 V0 V3 COM0 V2 COM1 pin V1 V0 V3 V2 SEG0 pin V1 V0 SEG1 SEG0 SEG2 SEG3 V3 V2 SEG1 pin V1 V0 V3 V2 V1 V0 COM0-SEG0 segment voltage (active) -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 segment voltage (inactive) -V1 2 Frames -V2 -V3 1 Segment Time Note: 1 Frame = 2 single segment times. DS41569A-page 206 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 19-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 pin V1 V0 V2 COM2 COM1 pin V1 V0 COM1 V2 COM0 COM2 pin V1 V0 V2 SEG0 and SEG2 pins V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG1 pin V2 V1 V0 COM0-SEG0 segment voltage (inactive) -V1 -V2 V2 V1 V0 COM0-SEG1 segment voltage (active) -V1 -V2 1 Frame 1 Segment Time Note: 2011 Microchip Technology Inc. 1 Frame = 2 single segment times.
PIC16LF1904/6/7 FIGURE 19-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 pin V1 V0 COM2 V2 COM1 pin V1 COM1 V0 COM0 V2 COM2 pin V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 pin V2 SEG1 pin V1 V0 V2 V1 V0 COM0-SEG0 segment voltage (inactive) -V1 -V2 V2 V1 V0 COM0-SEG1 segment voltage (active) -V1 -V2 2 Frames 1 Segment Time Note: DS41569A-page 208 1 Frame = 2 single segment times. Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 19-15: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 pin V1 V0 V3 COM2 V2 COM1 pin V1 COM1 V0 COM0 V3 V2 COM2 pin V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 and SEG2 pins V3 V2 SEG1 pin V1 V0 V3 V2 V1 V0 COM0-SEG0 segment voltage (inactive) -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 segment voltage (active) -V1 -V2 -V3 1 Frame 1 Segment Time Note: 2011 Microchip Technology Inc. 1 Frame = 2 single segment times.
PIC16LF1904/6/7 FIGURE 19-16: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 pin V1 V0 V3 COM2 V2 COM1 pin V1 COM1 V0 COM0 V3 V2 COM2 pin V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 pin V3 V2 SEG1 pin V1 V0 V3 V2 V1 V0 COM0-SEG0 segment voltage (inactive) -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 segment voltage (active) -V1 -V2 -V3 2 Frames 1 Segment Time Note: DS41569A-page 210 1 Frame = 2 single segment times. Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 19-17: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 pin V3 V2 V1 V0 COM1 pin V3 V2 V1 V0 COM2 pin V3 V2 V1 V0 COM3 pin V3 V2 V1 V0 SEG0 pin V3 V2 V1 V0 SEG1 pin V3 V2 V1 V0 SEG0 SEG1 COM0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG0 segment voltage (active) COM0-SEG1 segment voltage (inactive) 1 Frame V3 V2 V1 V0 -V1 -V2 -V3 1 Segment Time Note: 1 Frame = 2 single segment times. 2011 Microchip Technology Inc.
PIC16LF1904/6/7 FIGURE 19-18: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM0 pin V3 V2 V1 V0 COM1 pin V3 V2 V1 V0 COM2 pin V3 V2 V1 V0 COM3 pin V3 V2 V1 V0 SEG0 pin V3 V2 V1 V0 SEG1 pin V3 V2 V1 V0 COM2 COM1 SEG0 SEG1 COM0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG0 segment voltage (active) COM0-SEG1 segment voltage (inactive) 2 Frames V3 V2 V1 V0 -V1 -V2 -V3 1 Segment Time Note: DS41569A-page 212 1 Frame = 2 single segment times. Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 19.10 LCD Interrupts The LCD module provides an interrupt in two cases. An interrupt when the LCD controller goes from active to inactive controller. An interrupt also provides unframe boundaries for Type B waveform. The LCD timing generation provides an interrupt that defines the LCD frame timing. 19.10.1 LCD INTERRUPT ON MODULE SHUTDOWN An LCD interrupt is generated when the module completes shutting down (LCDA goes from ‘1’ to ‘0’). 19.10.
PIC16LF1904/6/7 FIGURE 19-19: WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE (EXAMPLE – TYPE-B, NON-STATIC) LCD Interrupt Occurs Controller Accesses Next Frame Data COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 V3 V2 V1 V0 COM3 2 Frames TFINT Frame Boundary Frame Boundary TFWR Frame Boundary TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2 TFINT = (TFWR/2 – (2 TCY + 40 ns)) minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns) (TFWR/2 – (1 TCY + 40 ns)) maximum = 1.
PIC16LF1904/6/7 19.11 Operation During Sleep The LCD module can operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current Consumption mode.
PIC16LF1904/6/7 FIGURE 19-20: SLEEP ENTRY/EXIT WHEN SLPEN = 1 V3 V2 V1 COM0 V0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 SEG0 2 Frames SLEEP Instruction Execution DS41569A-page 216 Preliminary Wake-up 2011 Microchip Technology Inc.
PIC16LF1904/6/7 19.12 Configuring the LCD Module 19.14 LCD Current Consumption The following is the sequence of steps to configure the LCD module. When using the LCD module the current consumption consists of the following three factors: 1. • Oscillator Selection • LCD Bias Source • Capacitance of the LCD segments 2. 3. 4. 5. 6. 7. Select the frame clock prescale using bits LP<3:0> of the LCDPS register. Configure the appropriate pins to function as segment drivers using the LCDSEn registers.
PIC16LF1904/6/7 TABLE 19-9: Name SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTF IOCIF INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF LCDCON LCDEN SLPEN WERR — CS1 CS0 LMUX<1:0> 72 187 — — — — — LCDDATA0 SEG7 COM0 SEG6 COM0 SEG5 COM0 SEG4 COM0 SEG3 COM0 SEG2 COM0 SEG1 COM0 SEG0 COM0 191 LCDDATA1 SEG15 COM0 SEG14 COM0 SEG13 COM0 SEG12 COM0 SEG11 COM0 SEG10 COM0 SEG9 COM0 SEG8 COM0 191 LCDDATA2 SEG23 COM0 S
PIC16LF1904/6/7 20.0 Some programmers produce VPP greater than VIHH (9.0V), an external circuit is required to limit the VPP voltage. See Figure 20-1 for example circuit. IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware.
PIC16LF1904/6/7 20.2 FIGURE 20-2: Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC16LF1904/6/7 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. VDD Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2.
PIC16LF1904/6/7 For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 20-4 for more information.
PIC16LF1904/6/7 NOTES: DS41569A-page 222 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 21.0 INSTRUCTION SET SUMMARY 21.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.
PIC16LF1904/6/7 FIGURE 21-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal
PIC16LF1904/6/7 TABLE 21-3: PIC16LF1904/6/7 ENHANCED INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift C
PIC16LF1904/6/7 TABLE 21-3: PIC16LF1904/6/7 ENHANCED INSTRUCTION SET (CONTINUED) Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS 2 2 2 2 2 2 2 2 BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operat
PIC16LF1904/6/7 21.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND.
PIC16LF1904/6/7 BCF Bit Clear f Syntax: [ label ] BCF f,b BTFSC Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
PIC16LF1904/6/7 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16LF1904/6/7 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16LF1904/6/7 LSLF Logical Left Shift f {,d} MOVF Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16LF1904/6/7 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: MOVLP Move literal to PCL
PIC16LF1904/6/7 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None No Operation Syntax: [
PIC16LF1904/6/7 RETFIE Return from Interrupt Syntax: [ label ] RETURN RETFIE Return from Subroutine Syntax: [ label ] None RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16LF1904/6/7 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’.
PIC16LF1904/6/7 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16LF1904/6/7 22.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias....................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS .............................................................................................
PIC16LF1904/6/7 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) FIGURE 22-1: 3.6 EC Mode Only 2.5 Internal Oscillator or EC Mode 2.3 2.0 1.8 0 10 4 20 16 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 22-1 for each Oscillator mode’s supported frequencies. FIGURE 22-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 + 15% Temperature (°C) 85 60 ± 10% 25 0 -20 -40 1.8 + 15% 2.0 2.5 3.0 3.
PIC16LF1904/6/7 22.1 DC Characteristics: PIC16LF1904/6/7-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16LF1904/6/7 Param. No. Sym. Characteristic Min. Typ† Max. Units Conditions Supply Voltage D001 VDD 1.8 — 3.6 V FOSC 16 MHz: D002* VDR RAM Data Retention Voltage(1) 1.5 — — V Device in Sleep mode D002A* VPOR* Power-on Reset Release Voltage — 1.
PIC16LF1904/6/7 22.2 DC Characteristics: PIC16LF1904/6/7-I/E (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16LF1904/6/7 Param No. Supply Current (IDD) D010 D011 D011A D012 D013 D014 D015 D016 Note 1: 2: 3: Conditions Device Characteristics Min. Typ† Max. Units VDD Note (1, 2) — 45 75 A 1.8 — 80 140 A 3.0 — 100 160 A 3.6 — 130 200 A 1.
PIC16LF1904/6/7 22.3 DC Characteristics: PIC16LF1904/6/7-I/E (Power-Down) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended PIC16LF1904/6/7 Param No. Device Characteristics Power-down Base Current D023 D024 D025 Min. Typ† Conditions Max. +85°C Max. +125°C Units — 0.03 1.0 3.0 A 1.8 — 0.04 2.0 4.0 A 3.0 — 0.09 3.0 5.0 A 3.6 — 0.3 2.0 4.0 A 1.8 — 0.5 3.0 5.0 A 3.
PIC16LF1904/6/7 22.4 DC Characteristics: PIC16LF1904/6/7-I/E DC CHARACTERISTICS Param No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Min. Typ† Max. Units Conditions Input Low Voltage I/O PORT: D032 with TTL buffer — — 0.15 VDD V 1.8V VDD 3.6V D033 with Schmitt Trigger buffer — — 0.2 VDD V 1.8V VDD 3.6V — — 0.2 VDD V 0.25 VDD + 0.8 — — V 1.
PIC16LF1904/6/7 22.5 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP/RE3 pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA VDD for Bulk Erase 2.7 — VDD max. V D112 D113 VPEW VDD for Write or Row Erase VDD min. — VDD max.
PIC16LF1904/6/7 22.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. TH01 TH02 Sym. Characteristic JA Thermal Resistance Junction to Ambient JC TH03 TJMAX TH04 PD TH05 Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Typ.
PIC16LF1904/6/7 22.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16LF1904/6/7 22.8 AC Characteristics: PIC16LF1904/6/7-I/E TABLE 22-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ† Max. Units Conditions DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) EC Oscillator mode (high) DC — 32 MHz OS02 TOSC External CLKIN Period(1) 31.
PIC16LF1904/6/7 FIGURE 22-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 22-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym.
PIC16LF1904/6/7 FIGURE 22-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
PIC16LF1904/6/7 FIGURE 22-8: MINIMUM PULSE WIDTH FOR LPBOR DETECTION VDDIO (Monitored Voltage) VULPBOR VBPW < 10 nVs Pulse Rejected 2011 Microchip Technology Inc.
PIC16LF1904/6/7 TABLE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 10 18 27 ms VDD = 3.
PIC16LF1904/6/7 TABLE 22-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width Min. No Prescaler TT0L T0CKI Low Pulse Width No Prescaler TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler — — ns — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.
PIC16LF1904/6/7 TABLE 22-6: PIC16LF1904/6/7 A/D CONVERTER (ADC) CHARACTERISTICS: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — — ±1.7 AD03 EDL Differential Error — — ±1 LSb No missing codes VREF = 3.0V AD04 EOFF Offset Error — — ±2 LSb VREF = 3.0V AD05 EGN LSb VREF = 3.
PIC16LF1904/6/7 FIGURE 22-10: PIC16LF1904/6/7 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 1 TCY (TOSC/2(1)) AD131 Q4 AD130 A/D CLK 7 A/D Data 6 5 4 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16LF1904/6/7 NOTES: DS41569A-page 254 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 23.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS Graphs and charts are not available at this time. 2011 Microchip Technology Inc.
PIC16LF1904/6/7 NOTES: DS41569A-page 256 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 24.0 DEVELOPMENT SUPPORT 24.
PIC16LF1904/6/7 24.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 24.
PIC16LF1904/6/7 24.7 MPLAB SIM Software Simulator 24.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC16LF1904/6/7 24.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 24.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC16LF1904/6/7 25.0 PACKAGING INFORMATION 25.1 Package Marking Information 28-Lead PDIP Example PIC16LF1906-I/P 1048017 XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC (.300”) Example PIC16LF1906-E/SO e3 1048017 XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP (.209”) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC16LF1906 -E/SS e3 1048017 28-Lead UQFN (4x4x0.5 mm) Example XXXXX XXXXXX XXXXXX YWWNNN Legend: XX...
PIC16LF1904/6/7 Package Marking Information (Continued) 40-Lead PDIP (.600”) Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN PIC16F1904 -I/P e3 1010017 Example 40-Lead UQFN (5x5mm) XXXXXXX XXXXXXX XXXXXXX YYWWNNN 16F1904 -I/MV e3 1010017 44-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
PIC16LF1904/6/7 25.2 Package Details The following sections give the technical details of the packages. 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N E1 NOTE 1 1 2 3 D E A2 A L c b1 A1 e b eB 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PIC16LF1904/6/7 ! " !" # $ %&' !" ( 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 3 e b h α h c φ A2 A L A1 β L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7: 7 ; < & : 8 & = = = = = - # # 4 4 !! & # %% + 1 , : > #& . # # 4 > #& .
PIC16LF1904/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16LF1904/6/7 !)* + ! " !! '&, !!" 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 1 2 b NOTE 1 e c A2 A φ A1 L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = ? < & # %% = = : > #& . < < # # 4 > #& .
PIC16LF1904/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16LF1904/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41569A-page 268 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16LF1904/6/7 - 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; & & 7: 1 , = = = 1 ! & & = = .
PIC16LF1904/6/7 -- .) / 0 1 + . 2 32 32 $ & ./0 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 6 &! ' ! 9 ' &! 7"') % 9 #! 99 . .
PIC16LF1904/6/7 -- .) / 0 1 + . 2 32 32 $ & ./0 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 DS41569A-page 272 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16LF1904/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41569A-page 274 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2011 Microchip Technology Inc.
PIC16LF1904/6/7 NOTES: DS41569A-page 276 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 APPENDIX A: DATA SHEET REVISION HISTORY Revision A Original release (03/2011). 2011 Microchip Technology Inc.
PIC16LF1904/6/7 NOTES: DS41569A-page 278 Preliminary 2011 Microchip Technology Inc.
PIC16LF1904/6/7 INDEX A A/D Specifications............................................................ 252 Absolute Maximum Ratings .............................................. 237 AC Characteristics Industrial and Extended ............................................ 246 Load Conditions ........................................................ 245 ADC .................................................................................. 125 Acquisition Requirements .........................................
PIC16LF1904/6/7 Setting up 9-bit Mode with Address Detect....... 162 Transmitter........................................................ 157 Baud Rate Generator (BRG) Associated Registers ........................................ 168 Auto Baud Rate Detect ..................................... 172 Baud Rate Error, Calculating ............................ 167 Baud Rates, Asynchronous Modes................... 169 Formulas ...........................................................
PIC16LF1904/6/7 Frame Frequency...................................................... 200 Interrupts................................................................... 213 LCDCON Register .................................................... 185 LCDPS Register........................................................ 185 Multiplex Types ......................................................... 200 Operation During Sleep ............................................ 215 Pixel Control.............................
PIC16LF1904/6/7 R RCREG ............................................................................. 162 RCREG Register................................................................. 32 RCSTA Register.......................................................... 32, 165 Reader Response ............................................................. 286 Read-Modify-Write Operations.......................................... 223 Register RCREG Register.......................................................
PIC16LF1904/6/7 CLKOUT and I/O....................................................... 247 INT Pin Interrupt.......................................................... 70 Internal Oscillator Switch Timing................................. 62 LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 214 LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 216 Reset Start-up Sequence............................................ 53 Reset, WDT, OST and Power-up Timer ................... 248 Send Break Character Sequence ...
PIC16LF1904/6/7 NOTES: DS41569A-page 284 Preliminary 2011 Microchip Technology Inc.
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