Datasheet

 2000 Microchip Technology Inc. Preliminary DS40197B-page 41
PIC16HV540
7.9 Time-out Sequence and Power-down
Status Bits (TO/PD/PCWUF)
The TO, PD and PCWUF bits in the STATUS register
can be tested to determine if a RESET condition has
been caused by a power-up condition, a MCLR
, Watch-
dog Timer (WDT) Reset, WDT Wake-up Reset, or
Wake-up from SLEEP on Pin Change.
These STATUS bits are only affected by events listed in
Tabl e 7- 8.
Table 7-3 lists the reset conditions for the special func-
tion registers, while Table 7-4 lists the reset conditions
for all the registers.
7.10 Power-down Mode (SLEEP)
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
7.10.1 SLEEP
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO
bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared, the PCWUF bit
(STATUS<7>) is set and the oscillator driver is turned
off. The I/O ports maintain the status they had before
the SLEEP instruction was executed (driving high, driv-
ing low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR
/VPP pin low.
For lowest current consumption while powered down,
the T0CKI input should be at V
DD or VSS and the MCLR/
V
PP pin must be at a logic high level (VIH MCLR).
7.10.2 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. An external reset input on MCLR
/VPP pin.
2. A Watchdog Timer Time-out Reset (if WDT was
enabled).
3. A change on input pins PORTB:<0-3,7> when
Wake-up on Pin Change is enabled.
4. Brown-out Reset.
These events cause a device RESET. The TO
and PD
and PCWUF bits can be used to determine the cause
of device RESET. The TO
bit is cleared if a WDT time-
out occurred (and caused wake-up). The PD
bit, which
is set on power-up, is cleared when SLEEP is invoked.
The PCWUF
bit indicates a change in state while in
SLEEP at pins PORTB:<0-3,7> (since the SLEEP state
was entered).
The WDT is cleared when the device wakes from
SLEEP, regardless of the wake-up source.
TABLE 7-7: TO/PD/PCWUF STATUS
AFTER RESET
PCWUF TO PD RESET was caused by
111Power-up (POR)
uuuMCLR
Reset (normal operation)
(1)
u10MCLR Wake-up Reset (from SLEEP)
u01WDT Reset (normal operation)
u00WDT Wake-up Reset (from SLEEP)
0uuWake-up from SLEEP on Pin Change
xxxBrown-out Reset
Legend: u = unchanged, x = unknown
Note 1: The TO
and PD and PCWUF bits maintain their status (u)
until a reset occurs. A low-pulse on the MCLR
input does
not change the TO
and PD and PCWUF status bits.
TABLE 7-8: EVENTS AFFECTING TO/PD
STATUS BITS
Event PCWUF TO PD Remarks
Power-up 1 11
WDT Time-out u 0 u No effect on
PD
SLEEP instruction 1 10
CLRWDT instruction u 11
Wake-up from SLEEP
on Pin Change
0 uu
Legend: u = unchanged
Note: A WDT time-out will occur regardless of the status of the TO
bit. A SLEEP instruction will be executed, regardless of the
status of the PD
bit. Table 7-7 reflects the status of TO and PD
after the corresponding event.