Datasheet
2000 Microchip Technology Inc. Preliminary DS40197B-page 39
PIC16HV540
FIGURE 7-11: BROWN-OUT SITUATIONS
7.7 Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKIN pin. That means that the
WDT will run even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation or SLEEP, a WDT Reset or Wake-up Reset
generates a device RESET.
The TO
bit (STATUS<4>) will be cleared upon a Watch-
dog Timer Reset.
The Watchdog Timer is enabled/disabled by a device
configuration bit (see Figure 7-1). If the WDT is
enabled, software execution may not disable this func-
tion. When the WDTEN configuration bit is cleared, the
SWDTEN
bit, OPTION2<4>, enables/disables the
operation of the WDT.
7.7.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writ-
ing to the OPTION register. Thus, time-out a period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, V
DD and part-to-part process
variations (see DC specs).
Under worst case conditions (V
DD = Min., Temperature
= Max., max. WDT prescaler), it may take several sec-
onds before a WDT time-out occurs.
7.7.2 WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the max-
imum SLEEP time before a WDT Wake-up Reset.
7.8 Internal Voltage Regulators
The PIC16HV540 has 2 internal voltage regulators.
The PORTA I/O pads and OSC2 are powered by one
internal voltage regulator V
IO
, while the second internal
voltage regulator V
REG
, powers the PICmicro
®
device
core. Both regulated voltage levels can be synchro-
nously switched in the active modes between 3V and
5V through bit “RL” in the OPTION2 register. In addi-
tion, the “SL” bit in the OPTION2 register can be used
to control the core’s regulated voltage level during
SLEEP mode. V
REG
regulates the 15V power applied
to the V
DD
pin.
The on-chip Brown-out Detect circuitry monitors the
CPU regulated voltage V
REG
, for determining if a
brown-out reset is generated (see Section 7.6 for more
details on the BOD).
The regulator circuits are identical in functional nature
but only the V
IO
regulator voltage can be measured,
externally (See Section 10.1 for V
IO
parameters). The
operational voltage range and pin loading requirements
must be considered to ensure proper system operation.
For example, if 3V regulation is implemented during the
SLEEP mode and 40mA is being sourced from PORTA,
the V
IO
regulation voltage may approach the specified
minimum voltage. This may be an issue to consider for
connections to external circuitry. Likewise, if zero cur-
rent is sourced from the PORTA pins, the regulation
18 ms
(2)
BVDD
(1)
VREG
Internal
Reset
VREG
Internal
Reset
VREG
Internal
Reset
18 ms
(2)
18 ms
(2)
18 ms
(2)
BVDD
(1)
BVDD
(1)
Note 1: BVDD depends on selection of bit ‘RL’ in OPTION2 SFR.
2: DRT time depends on which oscillator mode is selected and which reset state the part is in.