Datasheet

PIC16HV540
DS40197B-page 38 Preliminary  2000 Microchip Technology Inc.
7.5 Device Reset Timer (DRT)
In the PIC16HV540, the Device Reset Timer (DRT)
runs any time the device is powered up. DRT runs from
reset and varies based on oscillator selection (see
Table 7-5).
The DRT provides a fixed 18 ms nominal time-out on
reset. The DRT operates on an internal RC oscillator.
The processor is kept in RESET as long as the DRT is
active. The DRT delay allows Vdd to rise above Vdd
min., and for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the device in
a RESET condition for approximately 18 ms after the
voltage on the MCLR
/VPP pin has reach a logic high
(V
IH) level. Thus, external RC networks connected to
the MCLR
input are not required in most cases, allow-
ing for savings in cost-sensitive and/or space restricted
applications.
The Device Reset time delay will vary from chip to chip
due to V
DD, temperature, and process variation. See
AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out, MCLR
Reset, Wake-up from SLEEP on Pin
Change and Brown-out Reset. When the external RC
oscillator mode is selected, all DRT periods, after the
initial POR, are 1 ms (typical).
TABLE 7-5: DRT (DEVICE RESET TIMER
PERIOD)
7.6 Brown-Out Detect (BOD)
The PIC16HV540 has on-chip Brown-out Detect cir-
cuitry. If enabled and if the internal power, V
REG,
falls
below parameter B
VDD
(See Section 10.1 ), for greater
time than parameter T
BOD
(See Table 10-3) the brown-
out condition will reset the chip. A reset is not guaran-
teed if V
REG
falls below B
VDD
for less time than param-
eter (T
BOD
).
On resets (Brown-out, Watchdog, MCLR
and Wake-up
on Pin Change), the chip will remain in reset until V
REG
rises above B
VDD
. Once the B
VDD
threshold has been
met the DRT will now be invoked and will keep the chip
in reset an additional 18mS (LP, XT and HS oscillator
modes) or 1mS for EXTRC.
If V
REG
drops below B
VDD
while the DRT is running, the
chip will go back into a Brown-out Reset and the DRT
will be re-initialized. Once V
REG
rises above the B
VDD
,
the DRT will execute the specified time period.
Figure 7-11 shows typical Brown-out situations.
The Brown-out Detect circuit can be disabled or
enabled by setting the BODEN
bit in the OPTION2
SFR. The Brown-out Detect is disabled upon all Power-
on Resets (POR).
7.6.1 IMPLEMENTING THE ON-CHIP BOD
CIRCUIT
The PIC16HV540 BOD circuitry differs from “conven-
tional” brown-out detect circuitry in that the BOD cir-
cuitry on the PIC16HV540 does not directly detect
“dips” in the external V
DD
supply voltage but rather the
internal V
REG
. The functionality of the BOD circuitry
ensures that program execution will halt and a reset
state will be entered into prior to the internal logic
becoming corrupted. The BOD circuit has two select-
able voltage settings, nominally 5V and 3V. Each regu-
lation voltage setting with its associated minimum and
maximum B
VDD
parameters has an intended opera-
tional mode that must be carefully considered.
For the 5V V
REG
setting, the minimum B
VDD
parameter
is 2.7V
.
This minimum B
VDD
voltage is below the part
V
DD
minimum requirements. This operational setting is
primarily intended for use when the PIC16HV540 is
operating at 4Mhz and V
DD
> 5.5V.
For the 3V V
REG
setting, the minimum B
VDD
parameter
is 1.8V.
This minimum B
VDD
voltage is below the part
V
DD
minimum requirements. This operational setting is
primarily intended for use when the PIC16HV540 is in
SLEEP. RAM retention is protected by the 1.8V trip
level.
For the regulation and Brown-out circuits to function as
intended the applied V
DD
is nominally 0.5V greater than
the regulation voltage setting.
Finally, if the internal brown-out circuit is deemed not to
meet system design requirements then an external
brown-out protection circuit may be required. Microchip
offers a complete family of voltage supervisor products
which can meet most design requirements.
Oscillator
Configuration
POR Reset
Subsequent
Resets
EXTRC 18 ms (typical) 1 ms (typical)
LP, XT & HS 18 ms (typical) 18 ms (typical)