PIC16HV540 Enhanced PIC16C54 EPROM-Based 8-Bit CMOS Microcontroller With On-Chip Voltage Regulator High-Performance RISC CPU: Pin Configurations Peripheral Features: 2000 Microchip Technology Inc.
PIC16HV540 Table of Contents 1.0 General Description ..................................................................................................................................... 3 2.0 PIC16HV540 Device Varieties ..................................................................................................................... 5 3.0 Architectural Overview ................................................................................................................................. 7 4.
PIC16HV540 1.0 GENERAL DESCRIPTION The PIC16HV540 from Microchip Technology is a lowcost, high-performance, 8-bit, fully-static, EPROMbased CMOS microcontroller. It is pin and software compatible with the PIC16C5X family of devices. It employs a RISC architecture with only 33 single word/ single cycle instructions. All instructions are single cycle except for program branches, which take two cycles.
PIC16HV540 1.2.6 TABLE 1-1: INCREASED STACK DEPTH The stack depth is 4 levels to allow modular program implementation by using functions and subroutines. 1.2.7 ENHANCED WATCHDOG TIMER (WDT) OPERATION The WDT is enabled by setting FUSE 2 in the configuration word. The WDT setting is latched and the fuse disabled during SLEEP mode to reduce current consumption. If the WDT is disabled by FUSE 2, it can be enabled/disabled under program control using bit 4 in OPTION2 Register (SWDTEN).
PIC16HV540 2.0 PIC16HV540 DEVICE VARIETIES 2.3 A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16HV540 Product Identification System at the back of this data sheet to specify the correct part number. For the PIC16HV540 family of devices, there is one device type, as indicated in the device number: 1. 2.
PIC16HV540 NOTES: DS40197B-page 6 Preliminary 2000 Microchip Technology Inc.
PIC16HV540 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC16HV540 can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16HV540 uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus.
PIC16HV540 FIGURE 3-1: PIC16HV540 BLOCK DIAGRAM VDD 3V/5V Regulator VREG 4 RB<3:0> RB7 FILTER BOD RL/SL PC (PIN CHANGE) SWDTEN (OPTION2 REGISTER) BODL/BODEN PCWU 9-11 T0CKI PIN STACK 1 9-11 EPROM 512 X 12 CONFIGURATION WORD “DISABLE” STACK 2 PC “OSC SELECT” STACK 3 12 INSTRUCTION REGISTER 9 12 2 WATCHDOG TIMER STACK 4 WDT TIME OUT “CODE PROTECT” OSCILLATOR/ TIMING & CONTROL CLKOUT WDT/TMR0 PRESCALER “SLEEP” 8 INSTRUCTION DECODER 6 6 “TRIS 7” FROM W FROM W 5 DIRECT RAM ADDR
PIC16HV540 TABLE 3-1: Name PINOUT DESCRIPTION - PIC16HV540 DIP, SOIC SSOP I/O/P Input No. No.
PIC16HV540 3.1 Clocking Scheme/Instruction Cycle 3.2 The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow is shown in Figure 3-2 and Example 3-1.
PIC16HV540 4.0 MEMORY ORGANIZATION 4.2.1 PIC16HV540 memory is organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one or two STATUS register bits. For devices with a data memory register file of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR).
PIC16HV540 TABLE 4-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-On Reset Value on MCLR and WDT Reset Value on Wake-up on Pin Change Value on Brown-Out Reset N/A TRIS I/O control registers (TRISA, TRISB) 1111 1111 1111 1111 1111 1111 1111 1111 N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler --11 1111 --11 1111 --11 1111 --11 1111 N/A OPTION2 Contains control bits to configure pin change
PIC16HV540 4.3 STATUS Register This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bits for program memories larger than 512 words. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16HV540 4.4 OPTION Register By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<5:0> bits. The OPTION register is a 6-bit wide, write-only register which contains various control bits to configure the Timer0/WDT prescaler and Timer0. EXAMPLE 4-1: movlw Example 4-1 illustrates how to initialize the OPTION register.
PIC16HV540 4.5 OPTION2 Register The OPTION2 register is a 6-bit wide, write-only register which contains various control bits to configure the added features on the PIC16HV540. A Power-on Reset sets the OPTION2<5:0> bits. Example 4-2 illustrates how to initialize the OPTION2 register. Note: All Power-on Resets will disable the Brown-out Detect circuit. All subsequent resets will not disable the Brown-out Detect if enabled.
PIC16HV540 4.6 Program Counter 4.6.1 As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC. For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. (Figure 4-3). For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word.
PIC16HV540 4.8 Indirect Data Addressing; INDF and FSR Registers The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a pointer). This is indirect addressing.
PIC16HV540 NOTES: DS40197B-page 18 Preliminary 2000 Microchip Technology Inc.
PIC16HV540 5.0 I/O PORTS 5.3 As with any other register, the I/O registers can be written and read under program control. However, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ports are defined as input (inputs are at hi-impedance) since the I/O control registers (TRISA, TRISB) are all set. 5.1 5.2 The output driver control registers are loaded with the contents of the W register by executing the TRIS f instruction.
PIC16HV540 FIGURE 5-1: BLOCK DIAGRAM OF PORTA<0:3> PINS DATA BUS D WR PORTA Q VIO Data Latch CK VIO Q P N W REG D TRIS PORTA RA0-RA3 pins Q TRIS Latch CK VSS VSS Q Reset RD PORTA FIGURE 5-2: BLOCK DIAGRAM OF PORTB<0:3> PINS DATA BUS D WR PORTB W REG Q VDD Data Latch Q CK D TRIS PORTB VDD Step-up Circuit VDD P Q TRIS Latch CK RB0-RB3 pins N Q VSS RD PORTB VSS Q Q D Step-down Circuit CK “SLEEP” RD PORTB WAKE-UP ON PIN CHANGE DS40197B-page 20 M U X Preliminary 2000
PIC16HV540 FIGURE 5-3: BLOCK DIAGRAM OF PORTB<4:6> PINS DATA BUS D WR PORTB W REG TRIS PORTB Q VDD Data Latch CK D VDD Q Step-up Circuit VDD P Q TRIS Latch CK RB4-RB6 pins N Q VSS RD PORTB VSS Step-down Circuit FIGURE 5-4: BLOCK DIAGRAM OF PORTB<7> PIN DATA BUS D WR PORTB W REG TRIS PORTB Q VDD Data Latch CK D VDD Q Step-up Circuit VDD P Q RB7 pin TRIS Latch CK N Q VSS RD PORTB VSS Step-down Circuit VDD P WAKE-UP ON PIN CHANGE 2000 Microchip Technology Inc.
PIC16HV540 TABLE 5-1: Address Name N/A TRIS 05h PORTA SUMMARY OF PORT REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I/O control registers (TRISA, TRISB) Value on Power-On Reset Value on MCLR and WDT Reset Value on Wake-up on Pin Change Value on Brown-Out Reset 1111 1111 1111 1111 1111 1111 1111 1111 — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu ---- uuuu ---- xxxx 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu uuuu uuuu xxxx xxxx 03h
PIC16HV540 FIGURE 5-5: SUCCESSIVE I/O OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Instruction fetched MOVWF PORTB PC + 1 MOVF PORTB,W Q1 Q2 Q3 Q4 PC + 2 PC + 3 NOP NOP This example shows a write to PORTB followed by a read from PORTB. RB7:RB0 Port pin written here Instruction executed 2000 Microchip Technology Inc.
PIC16HV540 NOTES: DS40197B-page 24 Preliminary 2000 Microchip Technology Inc.
PIC16HV540 6.0 TIMER0 MODULE AND TMR0 REGISTER Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1.
PIC16HV540 FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN RIN T0CKI pin FIGURE 6-3: PC (Program Counter) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC-1 PC T0 T0+1 Instruction Executed FIGURE 6-4: PC+2 PC+3 PC+4 PC+5 PC+6 T0+2 NT0 NT0 NT0 Write TMR0 executed Read TMR0 reads NT0 Read TMR0 reads NT0 NT0+1 Read TMR0 reads NT0 NT0+2 Read TMR0 Read TMR0 reads NT0 + 1 reads NT0 + 2 TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2 Q1 Q2 Q3 Q4 Q
PIC16HV540 6.1 When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4TOSC (and a small RC delay of 40 ns) divided by the prescaler value.
PIC16HV540 6.2 Prescaler EXAMPLE 6-2: An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT) (WDT postscaler not implemented on PIC16C52), respectively (Section 6.1.2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both.
PIC16HV540 FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER TCY ( = Fosc/4) Data Bus 0 T0CKI pin 1 M U X 8 1 M U X 0 T0SE(1) T0CS(1) 0 Watchdog Timer 0 TMR0 reg 7 PSA(1) 8-bit Prescaler M U X 1 Sync 2 Cycles 8 8 - to - 1MUX PS<2:0>(1) Internal Oscillator OSC2/ CLKOUT M U X Drive Circuit PSA(1) “SLEEP” 1 0 MUX WDTEN Configuration bit PSA(1) Oscillator Mode Select SWDTEN bit(2) WDT Time-Out Note 1: 2: 2000 Microchip Technology Inc.
PIC16HV540 NOTES: DS40197B-page 30 Preliminary 2000 Microchip Technology Inc.
PIC16HV540 7.0 SPECIAL FEATURES OF THE CPU The SLEEP mode is designed to offer a very low current power-down mode. The user can wake up from SLEEP through external reset or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.
PIC16HV540 7.2 Oscillator Configurations 7.2.1 OSCILLATOR TYPES FIGURE 7-2: The PIC16HV540 can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1:FOSC0) to select one of these four modes: • • • • OSC1 PIC16HV540 Clock from ext. system Open LP: XT: HS: RC: Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator Resistor/Capacitor Note: Not all oscillator selections available for all parts. See Section 7.1. 7.2.
PIC16HV540 7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT FIGURE 7-4: Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A welldesigned crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.
PIC16HV540 The Electrical Specifications sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).
PIC16HV540 TABLE 7-3: RESET CONDITIONS FOR SPECIAL REGISTERS PCL Addr: 02h Condition STATUS Addr: 03h 1111 1111 Power-on Reset 1111 1111 MCLR Reset (normal operation) 1111 1111 MCLR Wake-up (from SLEEP) 1111 1111 WDT Reset (normal operation) 1111 1111 WDT Wake-up (from SLEEP) 1111 1111 Wake-up from SLEEP on Pin Change 1111 1111 Brown-out Reset Legend: u = unchanged, x = unknown, - = unimplemented read as ’0’. Note 1: TO and PD bits retain their last value until one of the other reset conditions occur.
PIC16HV540 7.4 Power-On Reset (POR) FIGURE 7-7: The PIC16HV540 incorporates on-chip Power-on Reset (POR) circuitry which provides an internal chip reset for most power-up situations. To use this feature, the user merely ties the MCLR/VPP pin to VDD. A simplified block diagram of the on-chip Power-on Reset circuit is shown in Figure 7-7. The Power-on Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset.
PIC16HV540 FIGURE 7-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD) VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME V1 VDD MCLR INTERNAL POR TDRT DRT TIME-OUT INTERNAL RESET When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value.
PIC16HV540 7.5 Device Reset Timer (DRT) 7.6 In the PIC16HV540, the Device Reset Timer (DRT) runs any time the device is powered up. DRT runs from reset and varies based on oscillator selection (see Table 7-5). The DRT provides a fixed 18 ms nominal time-out on reset. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows Vdd to rise above Vdd min., and for the oscillator to stabilize.
PIC16HV540 FIGURE 7-11: BROWN-OUT SITUATIONS VREG BVDD(1) Internal Reset 18 ms(2) VREG BVDD(1) Internal Reset 18 ms(2) 18 ms(2) VREG BVDD(1) Internal Reset Note 1: 2: 7.7 18 ms(2) BVDD depends on selection of bit ‘RL’ in OPTION2 SFR. DRT time depends on which oscillator mode is selected and which reset state the part is in. 7.7.2 Watchdog Timer (WDT) The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components.
PIC16HV540 voltage may approach the maximum value. Again this condition should be considered when interfacing to external circuitry. In addition, the voltage level applied to the external VDD pin and operational temperature affects the internal regulation voltage.
PIC16HV540 7.9 Time-out Sequence and Power-down Status Bits (TO/PD/PCWUF) The TO, PD and PCWUF bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR, Watchdog Timer (WDT) Reset, WDT Wake-up Reset, or Wake-up from SLEEP on Pin Change.
PIC16HV540 7.11 Program Verification/Code Protection If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: 7.12 Microchip does not recommend code protecting windowed devices. ID Locations Four memory locations are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are readable and writable during program/verify.
PIC16HV540 8.0 INSTRUCTION SET SUMMARY Each PIC16HV540 instruction is a 12-bit word divided into an OPCODE, which specifies the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16HV540 instruction set summary in Table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode field descriptions.
PIC16HV540 TABLE 8-2: INSTRUCTION SET SUMMARY 12-Bit Opcode Mnemonic, Operands ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF Description MSb f,d f,d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Su
PIC16HV540 ADDWF Add W and f Syntax: [ label ] ADDWF ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (W) + (f) → (dest) Operation: (W) .AND. (f) → (dest) f,d Status Affected: C, DC, Z Encoding: 0001 Description: f,d Status Affected: Z Encoding: 0001 Add the contents of the W register and register ’f’. If ’d’ is 0 the result is stored in the W register. If ’d’ is ’1’ the result is stored back in register ’f’.
PIC16HV540 BSF Bit Set f Syntax: [ label ] BSF BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands: 0 ≤ f ≤ 31 0≤b≤7 Operands: 0 ≤ f ≤ 31 0≤b<7 Operation: 1 → (f) Operation: skip if (f) = 1 f,b Status Affected: None Status Affected: None Encoding: 0101 Description: Bit ’b’ in register ’f’ is set. Words: 1 Cycles: 1 Example: BSF bbbf ffff FLAG_REG, Encoding: 0111 Description: If bit ’b’ in register ’f’ is ’1’ then the next instruction is skipped.
PIC16HV540 CALL Subroutine Call CLRW Clear W Syntax: [ label ] CALL k Syntax: [ label ] CLRW Operands: 0 ≤ k ≤ 255 Operands: None Operation: (PC) + 1→ Top of Stack; k → PC<7:0>; (STATUS<6:5>) → PC<10:9>; 0 → PC<8> Operation: 00h → (W); 1→Z Status Affected: Z Status Affected: None Encoding: 1001 Description: Subroutine call. First, return address (PC+1) is pushed onto the stack. The eight bit immediate address is loaded into PC bits <7:0>.
PIC16HV540 COMF Complement f Syntax: [ label ] COMF Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) → (dest) f,d Status Affected: Z 0010 Description: The contents of register ’f’ are complemented. If ’d’ is 0 the result is stored in the W register. If ’d’ is 1 the result is stored back in register ’f’. Words: 1 Cycles: 1 Example: COMF 01df ffff = = Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – 1 → d; 0x13 0010 Description: The contents of register ’f’ are decremented.
PIC16HV540 INCF Increment f IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (f) + 1 → (dest) (W) .OR. (k) → (W) Operation: INCF f,d Status Affected: Z Status Affected: Z Encoding: 0010 Description: The contents of register ’f’ are incremented. If ’d’ is 0 the result is placed in the W register. If ’d’ is 1 the result is placed back in register ’f’.
PIC16HV540 MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) → (dest) MOVF f,d Encoding: 0010 Description: The contents of register ’f’ is moved to destination ’d’. If ’d’ is 0, destination is the W register. If ’d’ is 1, the destination is file register ’f’. ’d’ is 1 is useful to test a file register since status flag Z is affected.
PIC16HV540 OPTION Load OPTION Register RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: (W) → OPTION 0 ≤ f ≤ 31 d ∈ [0,1] Operation: See description below OPTION Status Affected: None Encoding: 0000 0000 0010 The content of the W register is loaded into the OPTION register. Words: 1 Cycles: 1 Encoding: 0011 Description: The contents of register ’f’ are rotated one bit to the left through the Carry Flag.
PIC16HV540 SLEEP Enter SLEEP Mode SUBWF Subtract W from f Syntax: [label] Syntax: [label] Operands: None Operands: Operation: 00h → WDT; 0 → WDT prescaler; 1 → TO; 0 → PD 1→ PCWUF 0 ≤ f ≤ 31 d ∈ [0,1] Operation: (f) – (W) → (dest) SLEEP Status Affected: C, DC, Z Encoding: Status Affected: TO, PD, PCWUF Encoding: 0000 Description: Time-out status bit (TO) is set. The power down status bit (PD) is cleared. The WDT and its prescaler are cleared.
PIC16HV540 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] SWAPF f,d Syntax: [label] Operands: 0 ≤ f ≤ 31 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 (f<3:0>) → (dest<7:4>); (f<7:4>) → (dest<3:0>) Operation: (W) .XOR. k → (W) Status Affected: Z Operation: Encoding: Status Affected: None XORLW k 1111 kkkk kkkk Description: The upper and lower nibbles of register ’f’ are exchanged. If ’d’ is 0 the result is placed in W register.
PIC16HV540 NOTES: DS40197B-page 54 Preliminary 2000 Microchip Technology Inc.
PIC16HV540 9.
PIC16HV540 9.4 MPLINK/MPLIB Linker/Librarian MPLINK is a relocatable linker for MPASM and MPLAB-C17 and MPLAB-C18. It can link relocatable objects from assembly or C source files along with precompiled libraries using directives from a linker script. MPLIB is a librarian for pre-compiled code to be used with MPLINK. When a routine from a library is called from another source file, only the modules that contains that routine will be linked in with the application.
PIC16HV540 9.10 PRO MATE II Universal Programmer The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant. The PRO MATE II has programmable VDD and VPP supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability.
PIC16HV540 9.16 PICDEM-17 The PICDEM-17 is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756, PIC17C762, and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included, and the user may erase it and program it with the other sample programs using the PRO MATE II or PICSTART Plus device programmers and easily debug and test the sample code.
Software Tools Emulators 2000 Microchip Technology Inc. Programmers Debugger á á á PIC16C5X á á á á á á á PIC14000 á á á á á á PIC12CXXX á á á á á á á PICSTARTPlus Low-Cost Universal Dev. Kit PRO MATE II Universal Programmer á á á á PIC16C8X á á á á á á á PIC16C7XX á á á á á á á PIC16C7X á á á á á á á PIC16F62X á á á PIC16CXXX á á á á á PIC16C6X á á á á á á á á Preliminary MCP2510 á á á á á á á á á á á á á á á á á á ® * Contact the Microchip Technology Inc.
PIC16HV540 NOTES: DS40197B-page 60 Preliminary 2000 Microchip Technology Inc.
PIC16HV540 10.0 ELECTRICAL CHARACTERISTICS - PIC16HV540 Absolute Maximum Ratings† Ambient temperature under bias.............................................................................................................. –20°C to +85°C Storage temperature ............................................................................................................................. –65°C to +150°C Voltage on VDD with respect to VSS ...........................................................................
PIC16HV540 10.1 DC Characteristics: PIC16HV540-04, 20 (Commercial) PIC16HV540-04I, 20I (Industrial) Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) DC Characteristics Power Supply Pins Characteristic Supply Voltage Typ.(1) Max. Units Sym. Min. Conditions VDD 3.5 4.5 — 15 15 V V LP, XT and RC modes HS mode RAM Data Retention Voltage(2) VDR — 1.
PIC16HV540 10.2 DC Characteristics: PIC16HV540-04, 20 (Commercial) PIC16HV540-04I, 20I (Industrial) DC Characteristics All Pins Except Power Supply Pins Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) Min. Typ.(1) Max. Units VSS VSS VSS VSS VSS VSS — — — — — — 0.10 VREG 0.10 VREG 0.10 VREG 0.10 VREG 0.3 VREG 0.10 VREG V V V V V V Pin at Hi-impedance 0.25 VREG+0.8V 0.85 VREG 0.85 VREG 4.5V 4.5V 0.
PIC16HV540 10.3 Timing Parameter Symbology and Load Conditions The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC16HV540 10.4 Timing Diagrams and Specifications FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16HV540 Q4 Q1 Q3 Q2 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16HV540 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature 0°C ≤ TA ≤ +70°C (commercial) –40°C ≤ TA ≤ +85°C (industrial) Parameter No. Sym.
PIC16HV540 FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16HV540 Q1 Q4 Q2 Q3 OSC1 10 11 CLKOUT 13 14 19 12 18 I/O Pin (input) 15 17 I/O Pin (output) New Value Old Value 20, 21 Note: All tests must be done with specified capacitive loads of 50 pF on I/O pins and CLKOUT.
PIC16HV540 FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16HV540 VDD MCLR 30 Internal POR 32 32 32 DRT Time-out Internal RESET Watchdog Timer RESET 31 34 34 I/O pin (Note 1) Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software. FIGURE 10-5: BROWN-OUT DETECT TIMING VREG 35 2000 Microchip Technology Inc.
PIC16HV540 TABLE 10-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16HV540 AC Characteristics Standard Operating Conditions (unless otherwise specified) 0°C ≤ TA ≤ +70°C (commercial) Operating Temperature –40°C ≤ TA ≤ +85°C (industrial) Parameter No. Sym 30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 15V, VREG = 5V 31 Twdt Watchdog Timer Time-out Period 9.0* 18* 40* ms VDD = 15V, VREG = 5V 32 TDRT Device Reset Timer Period 9.0* 0.55* 18* 1.1* 30* 2.
PIC16HV540 11.0 DC AND AC CHARACTERISTICS - PIC16HV540 The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only and devices will operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time.
PIC16HV540 FIGURE 11-7: TYPICAL IPD vs. VDD, WATCHDOG TIMER ENABLED (VIO = 5V) 8.0 900.0 800.0 700.0 600.0 500.0 400.0 300.0 200.0 100.0 0.0 R E XT = 10k 6.0 R E XT = 24k 0oC 5.0 4.0 25oC 3.0 85oC 2.0 R E XT = 100k 6 9 R E XT = 300k 3.5 6 9 12 15 VDD (V) 12 15 VDD (V) FIGURE 11-8: MAXIMUM IPD vs. VDD, WATCHDOG TIMER ENABLED (VIO = 5V) 9 FIGURE 11-5: TYPICAL IPD vs. VDD, WATCHDOG TIMER DISABLED (VIO = 5V) -40 oC 8 85 oC o -40 C 85 oC 3.5 IPD (uA) 7 4.0 I PD (uA) -40oC 7.
PIC16HV540 FIGURE 11-10: MAXIMUM IPD vs. VDD, WATCHDOG TIMER DISABLED (VIO = 3V) FIGURE 11-13: MAXIMUM IDD vs. FREQUENCY, WATCHDOG TIMER DISABLED, RC MODE (VDD = 15V, VIO = 5V, -40°C TO +85°C) 5 -40oC 4.5 1000 4 900 IPD (uA) 3.5 800 o 25 C 3 700 0oC 600 IDD (µA) 2.5 2 85oC 500 400 300 1.5 200 1 3.5 6 9 12 15 100 VDD (V) 0 0.5 FIGURE 11-11: TYPICAL IPD vs. VDD, WATCHDOG TIMER ENABLED (VIO = 3V) 4.50 IPD (uA) 4.00 -40oC 1 1.5 2 2.5 3 3.
PIC16HV540 FIGURE 11-15: IOH vs. VOH ON PORTA, VDD = 15V (VIO = 5V) 0 mi n8 5° C typi cal 25° C IOH (mA) -4 -6 -8 max -40° C -2 -10 -12 0 Note: 1 2 3 4 VOH (V) 5 6 7 Current being applied is being applied simultaneously to all 4 PORTA pins. FIGURE 11-16: IOH vs. VOH ON PORTA, VDD = 5V (VIO = 5V) 0 -2 al 2 5°C -6 typi c -8 -10 max -40° C mi n8 5°C IOH (mA) -4 -12 0 Note: 1 2 3 4 VOH (V) 5 6 Current being applied is being applied simultaneously to all 4 PORTA pins.
PIC16HV540 12.0 PACKAGING INFORMATION 12.1 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n α 1 E A2 A L c A1 B1 β p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .
PIC16HV540 12.2 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45 ° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .
PIC16HV540 12.3 18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP) E1 D W2 2 n 1 W1 E A2 A c L A1 eB B1 p B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § Window Width Window Length * Controlling Parameter § Significant Characteristic JEDEC Equivalent: MO-036 Drawing No.
PIC16HV540 12.4 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n α c A2 A φ L A1 β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .
PIC16HV540 12.5 Package Marking Information 18-Lead PDIP Example PIC16HV540 XXXXXXXXXXXXXXXXX 9923NNN XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX PIC16HV540 XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 9923NNN 18-Lead CERDIP Windowed Example PIC16HV5 XXXXXXXX 9923NNN XXXXXXXX XXXXXXXX YYWWNNN 20-Lead SSOP Example PIC16HV540 XXXXXXXXXXXX 9923NNN XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: MM...M XX...
PIC16HV540 NOTES: DS40197B-page 78 Preliminary 2000 Microchip Technology Inc.
PIC16HV540 INDEX A Absolute Maximum Ratings ......................................... 61 ALU ............................................................................ 7 Applications ................................................................. 3 Architectural Overview .................................................. 7 Assembler MPASM Assembler ............................................. 55 B Block Diagram On-Chip Reset Circuit .......................................... 35 PIC16C5X Series ........
PIC16HV540 Period ................................................................ 39 Programming Considerations ............................... 39 WWW, On-Line Support ................................................ 2 Z Zero bit ....................................................................... 7 DS40197B-page 80 Preliminary 2000 Microchip Technology Inc.
PIC16HV540 ON-LINE SUPPORT Systems Information and Upgrade Hot Line Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.
PIC16HV540 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC16HV540 PIC16HV540 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC16HV540 -XX X /XX XXX Pattern: QTP,SQTP, Code or Special Requirements JW SO P SS Package: Temperature Range: Windowed CERDIP SOIC PDIP SSOP - = –0°C to +70°C I = –40°C to +85°C Frequency 04 = 200 kHz (PICHV540-04) 04 = 4 MHz 20 = 20 MHz Range Device: = = = = PIC16HV540 PIC16HV540T :VDD range 3.5V to 15V :VDD range 3.
Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
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