Datasheet

PIC16F913/914/916/917/946
DS41250F-page 192 © 2007 Microchip Technology Inc.
FIGURE 13-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
TABLE 13-1: SUMMARY OF ASSOCIATED REGISTERS WITH DATA EEPROM
NameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0
Value on
POR, BOR
Value on
all other
Resets
INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1 EEIE
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 EEIF
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
EEADRH
— — —
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0
---0 0000 ---0 0000
EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 0000 0000
EECON1 EEPGD
— — — WRERR WREN WR RD 0--- x000 ---- q000
EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- ---- ----
EEDATH
— —
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
--00 0000 --00 0000
EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by data EEPROM module.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF EECON1,RD
executed here
INSTR(PC + 1)
executed here
Forced NOP
executed here
PC
PC + 1 EEADRH,EEADRL
PC+3
PC + 5
Flash ADDR
RD bit
EEDATH,EEDATL
P C + 3 PC + 4
INSTR (PC + 1)
INSTR(PC - 1)
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
Flash Data
EEDATH
EEDATL
register
EERHLT
INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)