Information

PIC16F91X/946

3. Module: Asynchronous Timer1

This Errata supersedes Errata DS80329.

When TImer1 is started or updated, the timer

needs to see a falling edge from the external clock

source before a rising edge can increment the

counter. If writes to TMR1H and TMR1L are not

completed while the external clock pulse is still

high, Timer1 will not count the first clock pulse after

the update.

When using an external crystal, the pulse width

from rising to falling edge is temperature

dependent and may decrease with temperature.

As a result, the timer may require an additional

oscillation to overflow.

Work around

Switching to the HFINTOSC after reloading, the

timer ensures the Timer1 will see a falling edge

before switching back to the external clock source.

Due to the time from Timer1 overflow to the reload

being application specific, wait for the timer to

increment before beginning the reload sequence.

This ensures the timer does not miss a rising edge

during reload.

EXAMPLE 1:

Affected Silicon Revisions

PIC16F913/914

PIC16F916/917

PIC16F946

BTFSC TMR1L,0

GOTO $-1

BTFSS TMR1L,0

GOTO $-1 ;Timer has just incremented, 31 μs before next rising edge to

;complete reload

Update:

BCF T1CON,TMR1CS ;Select HFINTOSC for Timer1

BSF TMR1H,7 ;Timer1 high byte 0x80

BCF T1CON,TMR1ON ;Timer1 off

BSF T1CON,TMR1CS ;Select external crystal

BCF T1CON,TMR1ON ;Timer1 on

Critical Timing of code sequence for instructions following last write to TMR1L or TMR1H.

A0 A1 A2 A3

XXX

A0 A1 A2 B0 B1 B2

XXXXXX

A0 A1