Datasheet

PIC16F913/914/916/917/946
DS41250F-page 30 © 2007 Microchip Technology Inc.
TABLE 2-3: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Page
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226
101h TMR0 Timer0 Module Register xxxx xxxx 99,226
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 40,226
103h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 32,226
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 41,226
105h WDTCON
— — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 235,227
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54,226
107h LCDCON LCDEN SLPEN
WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 145,227
108h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 146,227
109h LVDCON
— —IRVSTLVDEN— LVDL2 LVDL1 LVDL0 --00 -100 145,228
10Ah PCLATH
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 40,226
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 34,226
10Ch
EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 188,228
10Dh
EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 188,228
10Eh EEDATH
— —
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
--00 0000 188,228
10Fh EEADRH
— — —
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0
---0 0000 188,228
110h LCDDATA0 SEG7
COM0
SEG6
COM0
SEG5
COM0
SEG4
COM0
SEG3
COM0
SEG2
COM0
SEG1
COM0
SEG0
COM0
xxxx xxxx 147,228
111h LCDDATA1 SEG15
COM0
SEG14
COM0
SEG13
COM0
SEG12
COM0
SEG11
COM0
SEG10
COM0
SEG9
COM0
SEG8
COM0
xxxx xxxx 147,228
112h LCDDATA2
(2)
SEG23
COM0
SEG22
COM0
SEG21
COM0
SEG20
COM0
SEG19
COM0
SEG18
COM0
SEG17
COM0
SEG16
COM0
xxxx xxxx 147,228
113h LCDDATA3 SEG7
COM1
SEG6
COM1
SEG5
COM1
SEG4
COM1
SEG3
COM1
SEG2
COM1
SEG1
COM1
SEG0
COM1
xxxx xxxx 147,228
114h LCDDATA4 SEG15
COM1
SEG14
COM1
SEG13
COM1
SEG12
COM1
SEG11
COM1
SEG10
COM1
SEG9
COM1
SEG8
COM1
xxxx xxxx 147,228
115h LCDDATA5
(2)
SEG23
COM1
SEG22
COM1
SEG21
COM1
SEG20
COM1
SEG19
COM1
SEG18
COM1
SEG17
COM1
SEG16
COM1
xxxx xxxx 147,228
116h LCDDATA6 SEG7
COM2
SEG6
COM2
SEG5
COM2
SEG4
COM2
SEG3
COM2
SEG2
COM2
SEG1
COM2
SEG0
COM2
xxxx xxxx 147,228
117h LCDDATA7 SEG15
COM2
SEG14
COM2
SEG13
COM2
SEG12
COM2
SEG11
COM2
SEG10
COM2
SEG9
COM2
SEG8
COM2
xxxx xxxx 147,228
118h LCDDATA8
(2)
SEG23
COM2
SEG22
COM2
SEG21
COM2
SEG20
COM2
SEG19
COM2
SEG18
COM2
SEG17
COM2
SEG16
COM2
xxxx xxxx 147,228
119h LCDDATA9 SEG7
COM3
SEG6
COM3
SEG5
COM3
SEG4
COM3
SEG3
COM3
SEG2
COM3
SEG1
COM3
SEG0
COM3
xxxx xxxx 147,228
11Ah LCDDATA10 SEG15
COM3
SEG14
COM3
SEG13
COM3
SEG12
COM3
SEG11
COM3
SEG10
COM3
SEG9
COM3
SEG8
COM3
xxxx xxxx 147,228
11Bh
LCDDATA11
(2)
SEG23
COM3
SEG22
COM3
SEG21
COM3
SEG20
COM3
SEG19
COM3
SEG18
COM3
SEG17
COM3
SEG16
COM3
xxxx xxxx 147,228
11Ch LCDSE0
(3)
SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 147,228
11Dh LCDSE1
(3)
SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 147,228
11Eh LCDSE2
(2,3)
SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 147,228
11Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR
Reset and Watchdog Timer Reset during normal operation.
2: PIC16F914/917 and PIC16F946 only.
3: This register is only initialized by a POR or BOR reset and is unchanged by other Resets.