Datasheet

PIC16F913/914/916/917/946
DS41250F-page 282 © 2007 Microchip Technology Inc.
TABLE 19-16: I
2
C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
100* T
HIGH Clock high time
400 kHz mode 0.6 — μs Device must operate at a
minimum of 10 MHz
SSP Module 1.5T
CY —
101* T
LOW Clock low time 400 kHz mode 1.3 — μs Device must operate at a
minimum of 10 MHz
SSP Module 1.5T
CY —
102* T
R SDA and SCL rise
time
400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
103* T
F SDA and SCL fall time 400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
90* T
SU:STA Start condition setup
time
400 kHz mode 1.3 — μs Only relevant for Repeated
Start condition
91* T
HD:STA Start condition hold
time
400 kHz mode 0.6 — μs After this period the first clock
pulse is generated
106* T
HD:DAT Data input hold time 400 kHz mode 0 0.9 μs
107* T
SU:DAT Data input setup time 400 kHz mode 100 — ns (Note 2)
92* T
SU:STO Stop condition setup
time
400 kHz mode 0.6 — μs
109* T
AA Output valid from
clock
400 kHz mode — — ns (Note 1)
110* T
BUF Bus free time 400 kHz mode 1.3 — μs Time the bus must be free
before a new transmission
can start
C
B Bus capacitive loading — 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I
2
C bus device can be used in a Standard mode (100 kHz) I
2
C bus system, but the requirement
T
SU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line T
R max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I
2
C bus specification), before the SCL
line is released.