Datasheet

PIC16F913/914/916/917/946
DS41250F-page 232 © 2007 Microchip Technology Inc.
FIGURE 16-8: INT PIN INTERRUPT TIMING
TABLE 16-6: SUMMARY OF INTERRUPT REGISTERS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other Resets
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIR1
EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIR2
OSFIF C2IF C1IF LCDIF —LVDIF—CCP2IF0000 -0-0 0000 -0-0
PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2 OSFIE C2IE C1IE LCDIE
—LVDIE— CCP2IE 0000 -0-0 0000 -0-0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by the Interrupt
Module.
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
OSC1
CLKOUT
(3)
INT pin
INTF Flag
(INTCON reg.)
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency
PC
PC + 1
PC + 1
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (PC)
Inst (PC + 1)
Inst (PC - 1)
Inst (0004h)
Dummy Cycle
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 T
CY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(2)
(4)
(5)
(1)