Datasheet

PIC16F913/914/916/917/946
DS41250F-page 218 © 2007 Microchip Technology Inc.
15.3.4 OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
15.3.5 CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 4.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
15.3.6 EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
15.3.7 SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pin (CCPx) output drivers by
setting the associated TRIS bit.
2. Set the PWM period by loading the PR2 register.
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
4. Set the PWM duty cycle by loading the CCPRxL
register and CCPx bits of the CCPxCON register.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register.
• Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Enable PWM output after a new PWM cycle has
started:
• Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.
TABLE 15-5: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND PWM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
Resets
CCPxCON — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000
CCPRxL Capture/Compare/PWM Register X Low Byte xxxx xxxx uuuu uuuu
CCPRxH Capture/Compare/PWM Register X High Byte xxxx xxxx uuuu uuuu
CMCON1
— — — — — —
T1GSS C2SYNC ---- --10
---- --10
INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF
0000 000x 0000 000x
LCDCON LCDEN
SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE1
SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 0000 0000
PIE1
EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2
OSFIE C2IE C1IE LCDIE — LVDIE —CCP2IE0000 -0-0 0000 -0-0
PIR1
EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIR2
OSFIF C2IF C1IF LCDIF — LVDIF —CCP2IF0000 -0-0 0000 -0-0
RCSTA SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SSPCON
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 uuuu uuuu
T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
-000 0000 -000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR2 Timer2 Module Register 0000 0000 0000 0000
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TRISD
(1)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111
1111 1111
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare
and PWM.
Note 1: PIC16F914/917 and PIC16F946 only.