Datasheet

© 2007 Microchip Technology Inc. DS41250F-page 209
PIC16F913/914/916/917/946
FIGURE 14-12: CLOCK SYNCHRONIZATION TIMING
TABLE 14-4: SUMMARY OF REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on all
other
Resets
INTCON GIE PEIE
T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
LCDCON LCDEN
SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE1
SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 0000 0000
PIE1
EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IF TMR1IF 0000 0000 0000 0000
PIR1
EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
0000 0000 0000 0000
RCSTA SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x
0000 000x
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
SSPSTAT SMP
(1)
CKE
(1)
D/A PSR/WUA BF 0000 0000 0000 0000
TRISC TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the SSP module.
Note 1: Maintain these bits clear.
SDA
SCL
DX-1DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock