Datasheet

© 2007 Microchip Technology Inc. DS41250F-page 205
PIC16F913/914/916/917/946
FIGURE 14-9: I
2
C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)
SSPIF BF (SSPSTAT<0>)
Receive Data Byte
R/W
= 0
Receive First Byte of Address
Cleared in software
(PIR1<3>)
Cleared in software
Receive Second Byte of Address
Cleared by hardware when SSPADD is updated with low byte of address
UA (SSPSTAT<1>)
Clock is held low until update of SSPADD has taken place
UA is set indicating that the SSPADD needs to be updated
UA is set indicating that SSPADD needs to be updated
Cleared by hardware when SSPADD is updated with high byte of address
SSPBUF is written
with contents of SSPSR
Dummy read of SSPBUF to clear BF flag
CKP
Receive Data Byte
Bus master
terminates transfer
ACK
Cleared in software
Cleared in software
SSPOV (SSPCON<6>)
SSPOV is set because SSPBUF is still full. ACK
is not sent.
(CKP does not reset to ‘0’ when SEN = 0)
Clock is held low until update of SSPADD has taken place
SDA SCL
S
12345
6
789
123
4567
89
12345 78
9
P
1111
0
A9
A8
A7
A6 A5 A4
A3 A2 A1
A0
D7
D6
D5
D4
D3 D1
D0
ACK
ACK
D2
6
ACK
1
23
4
5789
D7
D6
D5
D4
D3
D1 D0D2
6
ACK
0