Datasheet

PIC16F913/914/916/917/946
DS41250F-page 204 © 2007 Microchip Technology Inc.
14.12.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W
bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK
) pulse is given. An overflow
condition is defined as either bit BF of the SSPSTAT
register is set, or bit SSPOV of the SSPCON register is
set. This is an error condition due to the user’s firm-
ware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF of the PIR1 register must be
cleared in software. The SSPSTAT register is used to
determine the status of the byte.
FIGURE 14-8: I
2
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
P
9
8
765
D0
D1
D2
D3
D4
D5D6
D7
S
A7
A6 A5 A4 A3 A2
A1
SDA
SCL
1
2
34 56 78
9123
4
56
7
89
12
34
Bus Master
terminates
transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK
Receiving Data
Receiving Data
D0
D1
D2
D3D4D5D6
D7
ACK
R/W = 0
Receiving Address
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
ACK
ACK is not sent.