Datasheet

PIC16F913/914/916/917/946
DS41250F-page 110 © 2007 Microchip Technology Inc.
FIGURE 8-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM
FIGURE 8-3: COMPARATOR C2 OUTPUT BLOCK DIAGRAM
DQ
EN
To C 1 O U T p i n
RD CMCON0
Set C1IF bit
MULTIPLEX
Port Pins
Q3*RD CMCON0
Reset
To D a ta Bu s
C1INV
DQ
EN
CL
Q1
Note 1: Q1 and Q3 are phases of the four-phase system clock (FOSC).
2: Q1 is held high during Sleep mode.
C1
C2SYNC
DQ
EN
To C2OUT pin
RD CMCON0
Set C2IF bit
MULTIPLEX
Port Pins
Q3*RD CMCON0
Reset
To Data Bus
C2INV
Timer1
clock source
(1)
0
1
To SYNCC2OUT
DQ
DQ
EN
CL
Q1
Note 1: Comparator output is latched on falling edge of Timer1 clock source.
2: Q1 and Q3 are phases of the four-phase system clock (F
OSC).
3: Q1 is held high during Sleep mode.
C2