PIC16F913/914/916/917/946 Data Sheet 28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology © 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F913/914/916/917/946 28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology High-Performance RISC CPU: Low-Power Features: • Only 35 instructions to learn: - All single-cycle instructions except branches • Operating speed: - DC – 20 MHz oscillator/clock input - DC – 200 ns instruction cycle • Program Memory Read (PMR) capability • Interrupt capability • 8-level deep hardware stack • Direct, Indirect and Relative Addressing modes • Standby Current: - <100 nA
PIC16F913/914/916/917/946 Program Memory Device Data Memory Flash (words/bytes) SRAM (bytes) EEPROM (bytes) 4K/7K 256 256 PIC16F913 I/O 10-bit A/D (ch) LCD (segment drivers) CCP Timers 8/16-bit 24 5 16(1) 1 2/1 PIC16F914 4K/7K 256 256 35 8 24 2 2/1 PIC16F916 8K/14K 352 256 24 5 16(1) 1 2/1 PIC16F917 8K/14K 352 256 35 8 24 2 2/1 PIC16F946 8K/14K 336 256 53 8 42 2 2/1 Note 1: COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG
PIC16F913/914/916/917/946 TABLE 1: PIC16F914/917 40-PIN SUMMARY I/O Pin A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic RA0 2 AN0 SEG12 C1- — — — — — — — RA1 3 AN1 SEG7 C2- — — — — — — — RA2 4 AN2/VREF- COM2 C2+ — — — — — — — RA3 5 AN3/VREF+ SEG15 C1+ — — — — — — — RA4 6 SEG4 C1OUT T0CKI — — — — — — RA5 7 SEG5 C2OUT — — — SS — — — AN4 RA6 14 — — — T1OSO — — — — — OSC2/CLKOUT RA7 13 — — — T
PIC16F913/914/916/917/946 Pin Diagrams – PIC16F913/916, 28-Pin 28-pin PDIP, SOIC, SSOP DS41250F-page 4 RB4/COM0 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RE3/MCLR/VPP RA0/AN0/C1-/SEG12 9 10 11 12 13 14 RC2/VLCD3 RC3/SEG6 RC4/T1G/SDO/SEG11 RC5/T1CKI/CCP1/SEG10 RC6/TX/CK/SCK/SCL/SEG9 RA6/OSC2/CLKOUT/T1OSO 6 7 RC1/VLCD2 RA7/OSC1/CLKIN/T1OSI 8 VSS PIC16F913/916 RC0/VLCD1 RA5/AN4/C2OUT/SS/SEG5 RB5/COM1 2 3 4 5 RA4/C1OUT/T0CKI/SEG4 22 1 26 25 24 23 RA2/AN2/C2+/VREF-/COM2 28
PIC16F913/914/916/917/946 TABLE 2: PIC16F913/916 28-PIN (PDIP, SOIC, SSOP) SUMMARY I/O Pin A/D LCD Comparators Timers CCP AUSART SSP RA0 2 AN0 SEG12 C1- — — — — RA1 3 AN1 SEG7 C2- — — — — RA2 4 AN2/VREF- COM2 C2+ — — — — RA3 5 AN3/VREF+ SEG15/ COM3 C1+ — — — Interrupt Pull-Up Basic — — — — — — — — — — — — — — RA4 6 — SEG4 C1OUT T0CKI — — — — — RA5 7 — SEG5 C2OUT — — — SS — — — RA6 10 — — — T1OSO — — — — — OSC2/CL
PIC16F913/914/916/917/946 TABLE 3: I/O Pin PIC16F913/916 28-PIN (QFN) SUMMARY A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic RA0 27 AN0 SEG12 C1- — — — — — — — RA1 28 AN1 SEG7 C2- — — — — — — — RA2 1 AN2/VREF- COM2 C2+ — — — — — — — RA3 2 AN3/VREF+ SEG15/ COM3 C1+ — — — — — — — — RA4 3 — SEG4 C1OUT T0CKI — — — — — RA5 4 AN4 SEG5 C2OUT — — — SS — — — RA6 7 — — — T1OSO — — — — — OSC2/CLKOUT RA7 6
PIC16F913/914/916/917/946 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 PIC16F914/917 NC RC0/VLCD1 RA6/OSC2/CLKOUT/T1OSO RA7/OSC1/CLKIN/T1OSI VSS VDD RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/C2OUT/SS/SEG5 RA4/C1OUT/T0CKI/SEG4 33 32 31 30 29 28 27 26 25 24 23 RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2 RD1 RD0/COM3 RC3/SEG6 RC2/VLCD3 RC1/VLCD2 RC0/VLDC1 1 2 3 4 5 6 7 8 9 10 11 PIC16F914/917 33 32 31 30 29 28 27 26 25 24 23 RA6/OSC2/CLKOUT/T1OS
PIC16F913/914/916/917/946 TABLE 4: I/O Pin PIC16F914/917 44-PIN (TQFP) SUMMARY A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic RA0 19 AN0 SEG12 C1- — — — — — — — RA1 20 AN1 SEG7 C2- — — — — — — — RA2 21 AN2/VREF- COM2 C2+ — — — — — — — RA3 22 AN3/VREF+ SEG15 C1+ — — — — — — — — RA4 23 — SEG4 C1OUT T0CKI — — — — — RA5 24 AN4 SEG5 C2OUT — — — SS — — — RA6 31 — — — T1OSO — — — — — OSC2/CLKOUT RA7 3
PIC16F913/914/916/917/946 TABLE 5: I/O Pin PIC16F914/917 44-PIN (QFN) SUMMARY A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic RA0 19 AN0 SEG12 C1- — — — — — — — RA1 20 AN1 SEG7 C2- — — — — — — — — RA2 21 AN2/VREF- COM2 C2+ — — — — — — RA3 22 AN3/VREF+ SEG15 C1+ — — — — — — — RA4 23 — SEG4 C1OUT T0CKI — — — — — — RA5 24 AN4 SEG5 C2OUT — — — SS — — — RA6 33 — — — T1OSO — — — — — OSC2/CLKOUT RA7 32
PIC16F913/914/916/917/946 RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RD0/COM3 RD1 RD2/CCP2 VDD VSS RD3/SEG16 RC4/T1G/SDO/SEG11 RC5/T1CKI/CCP1/SEG10 RC6/TX/CK/SCK/SCL/SEG9 RD4/SEG17 RD5/SEG18 64-pin TQFP RC7/RX/DT/SDI/SDA/SEG8 Pin Diagram – PIC16F946 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RD6/SEG19 RD7/SEG20 RG0/SEG36 RG1/SEG37 RG2/SEG38 RG3/SEG39 RG4/SEG40 RG5/SEG41 VSS VDD RF0/SEG32 RF1/SEG33 RF2/SEG34 RF3/SEG35 RB0/INT/SEG0 RB1/SEG1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC16F946 15
PIC16F913/914/916/917/946 TABLE 6: I/O Pin PIC16F946 64-PIN (TQFP) SUMMARY A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic RA0 27 AN0 SEG12 C1- — — — — — — — RA1 28 AN1 SEG7 C2- — — — — — — — RA2 29 AN2/VREF- COM2 C2+ — — — — — — — RA3 30 AN3/VREF+ SEG15 C1+ — — — — — — — RA4 31 — SEG4 C1OUT T0CKI — — — — — — RA5 32 AN4 — C2OUT — — — SS — — — RA6 40 SEG5 — — T1OSO — — — — — OSC2/CLKOUT RA7 39
PIC16F913/914/916/917/946 TABLE 6: I/O Pin PIC16F946 64-PIN (TQFP) SUMMARY (CONTINUED) A/D LCD Comparators Timers CCP AUSART SSP Interrupt Pull-Up Basic RF3 14 — SEG35 — — — — — — — — RF4 45 — SEG28 — — — — — — — — RF5 46 — SEG29 — — — — — — — — RF6 47 — SEG30 — — — — — — — — RF7 48 — SEG31 — — — — — — — — RG0 3 — SEG36 — — — — — — — — RG1 4 — SEG37 — — — — — — — — RG2 5 — SEG38 — — — — — — — — RG3 6
PIC16F913/914/916/917/946 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Memory Organization ................................................................................................................................................................. 23 3.0 I/O Ports .........................................................................
PIC16F913/914/916/917/946 NOTES: DS41250F-page 14 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 1.0 DEVICE OVERVIEW The PIC16F91X/946 devices are covered by this data sheet. They are available in 28/40/44/64-pin packages. Figure 1-1 shows a block diagram of the PIC16F913/916 device, Figure 1-2 shows a block diagram of the PIC16F914/917 device, and Figure 1-3 shows a block diagram of the PIC16F946 device. Table 1-1 shows the pinout descriptions.
PIC16F913/914/916/917/946 FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM INT Configuration 13 8 Data Bus Program Counter PORTA RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 Flash 4K/8K x 14 Program RAM 256/352 bytes File Registers 8-Level Stack (13-bit) Memory Program 14 Bus Program Memory Read (PMR) 9 RAM Addr PORTB RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 Addr MUX Instruction Reg Direct Addr 7 8 Indirect Addr FSR Reg STATUS Reg 8 PORTC 3 Instruction Decode and Control Oscillator Start-up Timer OSC1/CLKIN OSC2/CL
PIC16F913/914/916/917/946 FIGURE 1-3: PIC16F946 BLOCK DIAGRAM INT PORTA Configuration 13 Program Counter RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 8 Data Bus Flash 8K x 14 Program RAM 336 x 8 bytes File Registers 8-Level Stack (13-bit) Memory Program 14 Bus Program Memory Read (PMR) 9 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RAM Addr Addr MUX Instruction Reg Direct Addr 7 8 Indirect Addr FSR Reg Power-up Timer Instruction Decode and Control Internal Oscillator Block 3 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7
PIC16F913/914/916/917/946 TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS Name RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3(1)/ SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 RA6/OSC2/CLKOUT/T1OSO RA7/OSC1/CLKIN/T1OSI RB0/INT/SEG0 Function Input Output Type Type RA0 TTL AN0 AN Description CMOS General purpose I/O. — Analog input Channel 0. C1- AN — Comparator 1 negative input. SEG12 — AN LCD analog output.
PIC16F913/914/916/917/946 TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED) Name RB1/SEG1 RB2/SEG2 RB3/SEG3 RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RC4/T1G/SDO/SEG11 RC5/T1CKI/CCP1/SEG10 Function Input Output Type Type RB1 TTL SEG1 — RB2 TTL SEG2 — RB3 TTL SEG3 — RB4 TTL COM0 — RB5 TTL Description CMOS General purpose I/O. Individually enabled pull-up. AN LCD analog output. CMOS General purpose I/O.
PIC16F913/914/916/917/946 TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED) Name RC6/TX/CK/SCK/SCL/SEG9 RC7/RX/DT/SDI/SDA/SEG8 Function RD1(2) RD2/CCP2(2) RD3/SEG16(2) RD4/SEG17(2) RD5/SEG18 RD6/SEG19 (2) (2) RD7/SEG20(2) RE0/AN5/SEG21(2) RE1/AN6/SEG22(2) RE2/AN7/SEG23(2) RE3/MCLR/VPP Description RC6 ST CMOS General purpose I/O. TX — CMOS USART asynchronous serial transmit. CK ST CMOS USART synchronous serial clock. SCK ST CMOS SPI clock. SCL ST(4) OD I2C™ clock.
PIC16F913/914/916/917/946 TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED) Name RE4/SEG24(3) RE5/SEG25 (3) RE6/SEG26(3) RE7/SEG27(3) RF0/SEG32(3) RF1/SEG33 (3) RF2/SEG34(3) RF3/SEG35(3) RF4/SEG28(3) RF5/SEG29 (3) RF6/SEG30(3) RF7/SEG31(3) RG0/SEG36(3) RG1/SEG37 (3) RG2/SEG38(3) RG3/SEG39(3) RG4/SEG40(3) (3) Function Input Output Type Type RE4 ST SEG24 — RE5 ST SEG25 — RE6 ST SEG26 — RE7 ST SEG27 — RF0 ST SEG32 — RF1 ST SEG33 — RF2 ST SEG34 — RF3 ST SEG35 —
PIC16F913/914/916/917/946 TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED) Name VSS Function VSS Input Output Type Type P — Description Ground reference for microcontroller. Legend: AN = Analog input or output TTL = TTL compatible input HV = High Voltage Note 1: 2: 3: 4: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946. Pins available on PIC16F914/917 and PIC16F946 only. Pins available on PIC16F946 only.
PIC16F913/914/916/917/946 2.0 MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F91X/946 has a 13-bit program counter capable of addressing a 4K x 14 program memory space for the PIC16F913/914 (0000h-0FFFh) and an 8K x 14 program memory space for the PIC16F916/ 917 and PIC16F946 (0000h-1FFFh). Accessing a location above the memory boundaries for the PIC16F913 and PIC16F914 will cause a wrap around within the first 4K x 14 space.
PIC16F913/914/916/917/946 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers (GPRs) and the Special Function Registers (SFRs). Bits RP0 and RP1 are bank select bits. RP1 RP0 0 0 → Bank 0 is selected 0 1 → Bank 1 is selected 1 0 → Bank 2 is selected 1 1 → Bank 3 is selected Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers.
PIC16F913/914/916/917/946 FIGURE 2-3: PIC16F913/916 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h PORTB 06h PORTC 07h 08h PORTE 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch PIR2 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h SSPBUF 13h SSPCON 14h CCPR1L 15h CCPR1H 16h CCP1CON 17h RCSTA 18h TXREG 19h RCREG 1Ah 1Bh 1Ch 1Dh ADRESH 1Eh ADCON0 1Fh 20h General Purpose Register File Address (1) Indirect addr.
PIC16F913/914/916/917/946 FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS File Address (1) Indirect addr. 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h PORTB 06h PORTC 07h PORTD 08h PORTE 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch PIR2 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h SSPBUF 13h SSPCON 14h CCPR1L 15h CCPR1H 16h CCP1CON 17h RCSTA 18h TXREG 19h RCREG 1Ah CCPR2L 1Bh CCPR2H 1Ch CCP2CON 1Dh ADRESH 1Eh ADCON0 1Fh 20h General Purpose Register File Address (1) Indirect addr.
PIC16F913/914/916/917/946 FIGURE 2-5: PIC16F946 SPECIAL FUNCTION REGISTERS File Address Indirect addr. (1) 00h TMR0 01h PCL 02h STATUS 03h FSR 04h PORTA 05h PORTB 06h PORTC 07h PORTD 08h PORTE 09h PCLATH 0Ah INTCON 0Bh PIR1 0Ch PIR2 0Dh TMR1L 0Eh TMR1H 0Fh T1CON 10h TMR2 11h T2CON 12h SSPBUF 13h SSPCON 14h CCPR1L 15h CCPR1H 16h CCP1CON 17h RCSTA 18h TXREG 19h RCREG 1Ah CCPR2L 1Bh CCPR2H 1Ch CCP2CON 1Dh ADRESH 1Eh ADCON0 1Fh 20h General Purpose Register File Address Indirect addr.
PIC16F913/914/916/917/946 TABLE 2-1: Addr PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226 01h TMR0 Timer0 Module Register xxxx xxxx 99,226 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 40,226 03h STATUS 0001 1xxx 32,226 IRP RP1 RP0 TO PD Z DC
PIC16F913/914/916/917/946 TABLE 2-2: Addr Name PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL 83h STATUS RBPU INTEDG T0CS xxxx xxxx 41,226 PSA PS2 PS1 PS0 1111 1111 33,227 0000 0000 40,226 TO PD Z DC C 0001 1xxx 32,226 T0SE Program Counter’s (PC) Least Sig
PIC16F913/914/916/917/946 TABLE 2-3: Addr Name PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226 101h TMR0 Timer0 Module Register xxxx xxxx 99,226 102h PCL Program Counter’s (PC) Least Significant Byte 103h STATUS 104h FSR 105h WDTCON IRP RP1 RP0 TO PD Z DC C WDTPS3
PIC16F913/914/916/917/946 TABLE 2-4: Addr PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page xxxx xxxx 41,226 Bank 3 180h INDF 181h Addressing this location uses contents of FSR to address data memory (not a physical register) OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 33,227 182h PCL 0000 0000 40,226 183h STATUS 184h FSR 185h TRISF(3) TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2
PIC16F913/914/916/917/946 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (SRAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F913/914/916/917/946 2.2.2.2 OPTION register Note: The OPTION register, shown in Register 2-2, is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External RB0/INT interrupt Timer0 Weak pull-ups on PORTB REGISTER 2-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit of the OPTION register to ‘1’. See Section 6.3 “Timer1 Prescaler”.
PIC16F913/914/916/917/946 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RB0/INT/SEG0 pin interrupts. REGISTER 2-3: R/W-0 INTCON: INTERRUPT CONTROL REGISTER R/W-0 GIE Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register.
PIC16F913/914/916/917/946 2.2.2.4 PIE1 Register The PIE1 register contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16F913/914/916/917/946 2.2.2.5 PIE2 Register The PIE2 register contains the interrupt enable bits, as shown in Register 2-5. REGISTER 2-5: Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
PIC16F913/914/916/917/946 2.2.2.6 PIR1 Register The PIR1 register contains the interrupt flag bits, as shown in Register 2-6. REGISTER 2-6: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F913/914/916/917/946 2.2.2.7 PIR2 Register The PIR2 register contains the interrupt flag bits, as shown in Register 2-7. REGISTER 2-7: Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F913/914/916/917/946 2.2.2.8 PCON Register The Power Control (PCON) register contains flag bits (see Table 16-2) to differentiate between a: • • • • Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset The PCON register also controls the software enable of the BOR. The PCON register bits are shown in Register 2-8.
PIC16F913/914/916/917/946 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-6 shows the two situations for the loading of the PC. The upper example in Figure 2-6 shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F913/914/916/917/946 2.5 Indirect Addressing, INDF and FSR Registers EXAMPLE 2-2: MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h.
PIC16F913/914/916/917/946 NOTES: DS41250F-page 42 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 3.0 I/O PORTS 3.1 The PIC16F913/914/916/917/946 family of devices includes several 8-bit PORT registers along with their corresponding TRIS registers and one four bit port: • • • • • • • PORTA and TRISA PORTB and TRISB PORTC and TRISC PORTD and TRISD(1) PORTE and TRISE PORTF and TRISF(2) PORTG and TRISG(2) ANSEL Register The ANSEL register (Register 3-1) is used to configure the Input mode of an I/O pin to analog.
PIC16F913/914/916/917/946 3.2 PORTA and TRISA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 3-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Example 3-1 shows how to initialize PORTA.
PIC16F913/914/916/917/946 3.2.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. 3.2.1.1 RA0/AN0/C1-/SEG12 Figure 3-1 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.2.1.2 RA1/AN1/C2-/SEG7 Figure 3-2 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.2.1.3 RA2/AN2/C2+/VREF-/COM2 Figure 3-3 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.2.1.4 RA3/AN3/C1+/VREF+/COM3/SEG15 Figure 3-4 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.2.1.5 RA4/C1OUT/T0CKI/SEG4 Figure 3-5 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.2.1.6 RA5/AN4/C2OUT/SS/SEG5 Figure 3-6 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.2.1.7 RA6/OSC2/CLKOUT/T1OSO Figure 3-7 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.2.1.8 RA7/OSC1/CLKIN/T1OSI Figure 3-8 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.3 PORTB and TRISB Registers PORTB is an 8-bit bidirectional I/O port. All PORTB pins can have a weak pull-up feature, and PORTB<7:4> implements an interrupt-on-input change function. PORTB is also used for the Serial Flash programming interface and ICD interface. EXAMPLE 3-2: BANKSEL CLRF BANKSEL MOVLW MOVWF PORTB PORTB TRISB 0FFh TRISB INITIALIZING PORTB ; ;Init PORTB ; ;Set RB<7:0> as inputs ; 3.
PIC16F913/914/916/917/946 REGISTER 3-4: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown RB<7:0>: PORTB I/O Pin bits 1 = Port pin is >VIH min. 0 = Port pin is
PIC16F913/914/916/917/946 REGISTER 3-7: WPUB: WEAK PULL-UP REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: x = Bit is unknown WPUB<7:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Global RBPU must be enabled for individual pull-ups to be
PIC16F913/914/916/917/946 3.4.3 PIN DESCRIPTIONS AND DIAGRAMS 3.4.3.2 Each PORTB pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or interrupts, refer to the appropriate section in this data sheet. 3.4.3.1 RB0/INT/SEG0 Figure 3-9 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.4.3.5 RB4/COM0 Figure 3-10 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.4.3.6 RB5/COM1 Figure 3-11 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.4.3.7 RB6/ICSPCLK/ICDCK/SEG14 Figure 3-12 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.4.3.8 RB7/ICSPDAT/ICDDAT/SEG13 Figure 3-13 shows the diagram for this pin.
PIC16F913/914/916/917/946 TABLE 3-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets 0000 000x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ---- LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu LCDSE1 SE15 SE14 SE13 SE
PIC16F913/914/916/917/946 3.5 PORTC and TRISC Registers EXAMPLE 3-3: PORTC is an 8-bit bidirectional port. PORTC is multiplexed with several peripheral functions. PORTC pins have Schmitt Trigger input buffers. All PORTC pins have latch bits (PORTC register). They will modify the contents of the PORTC latch (when written); thus, modifying the value driven out on a pin if the corresponding TRISC bit is configured for output.
PIC16F913/914/916/917/946 3.5.1 PIN DESCRIPTIONS AND DIAGRAMS 3.5.1.3 Each PORTC pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the LCD or SSP, refer to the appropriate section in this data sheet. 3.5.1.1 RC2/VLCD3 Figure 3-16 shows the diagram for this pin.
PIC16F913/914/916/917/946 FIGURE 3-15: Data Bus WR PORTC BLOCK DIAGRAM OF RC1 D CK VDD Q Q I/O Pin Data Latch D WR TRISC CK Q VSS Q TRIS Latch RD TRISC (VLCDEN and LMUX<1:0> ≠ 00) Schmitt Trigger RD PORTC (LCDEN and LMUX<1:0> ≠ 00) VLCD2 FIGURE 3-16: Data Bus WR PORTC BLOCK DIAGRAM OF RC2 D CK VDD Q Q I/O Pin Data Latch D WR TRISC CK Q VSS Q TRIS Latch VLCDEN RD TRISC Schmitt Trigger RD PORTC VLCD3 DS41250F-page 64 LCDEN © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 3.5.1.4 RC3/SEG6 Figure 3-17 shows the diagram for this pin. The RC3 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD FIGURE 3-17: BLOCK DIAGRAM OF RC3 Data Bus WR PORTC D CK VDD Q Q I/O Pin Data Latch D WR TRISC Q VSS Q CK TRIS Latch SE6 and LCDEN RD TRISC Schmitt Trigger RD PORTC SEG6 and LCDEN © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 3.5.1.5 RC4/T1G/SDO/SEG11 Figure 3-18 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.5.1.6 RC5/T1CKI/CCP1/SEG10 Figure 3-19 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.5.1.7 RC6/TX/CK/SCK/SCL/SEG9 Figure 3-20 shows the diagram for this pin.
PIC16F913/914/916/917/946 3.5.1.8 RC7/RX/DT/SDI/SDA/SEG8 Figure 3-21 shows the diagram for this pin.
PIC16F913/914/916/917/946 TABLE 3-3: Name CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu PORTC RC7 RC
PIC16F913/914/916/917/946 3.6 PORTD and TRISD Registers EXAMPLE 3-4: PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configured as an input or output. PORTD is only available on the PIC16F914/917 and PIC16F946.
PIC16F913/914/916/917/946 3.6.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTD pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. 3.6.1.1 RD0/COM3 Figure 3-22 shows the diagram for this pin. The RD0 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.6.
PIC16F913/914/916/917/946 FIGURE 3-22: BLOCK DIAGRAM OF RD0 VDD Data Bus WR PORTD D Q CK I/O Pin Q VSS Data Latch WR TRISD D Q CK Q TRIS Latch RD TRISD LCDEN and LMUX<1:0> = 11 Schmitt Trigger RD PORTD LCDEN and LMUX<1:0> = 11 COM3 FIGURE 3-23: BLOCK DIAGRAM OF RD1 VDD Data Bus WR PORTD D Q CK RD1 Pin Q VSS Data Latch WR TRISD D Q CK Q TRIS Latch RD TRISD Schmitt Trigger RD PORTD © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 3-24: BLOCK DIAGRAM OF RD2 (PORT/CCP2 Select) and CCPMX VDD CCP2 Data Out 0 Data Bus WR PORTD D Q CK Q 1 I/O Pin VSS Data Latch WR TRISD D Q CK Q TRIS Latch Schmitt Trigger RD TRISD RD PORTD CCP2 Input FIGURE 3-25: BLOCK DIAGRAM OF RD<7:3> VDD Data Bus WR PORTD D Q CK I/O Pin Q VSS Data Latch WR TRISD D Q CK Q TRIS Latch SE<20:16> and LCDEN RD TRISD Schmitt Trigger RD PORTD SEG<20:16> DS41250F-page 74 SE<20:16> and LCDEN © 2007 Microchip
PIC16F913/914/916/917/946 SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1) TABLE 3-4: Name CCP2CON(1) LCDCON LCDSE2(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets --00 0000 — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu PORTD(1) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu TRI
PIC16F913/914/916/917/946 3.7 EXAMPLE 3-5: PORTE and TRISE Registers PORTE is a 1-bit, 4-bit or 8-bit port with Schmitt Trigger input buffers. RE<7:4, 2:0> are individually configured as inputs or outputs and RE3 is only available as an input if MCLRE is ‘0’ in Configuration Word (Register 16-1). RE<2:0> are only available on the PIC16F914/917 and PIC16F946. RE<7:4> are only available on the PIC16F946.
PIC16F913/914/916/917/946 3.7.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTE pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions such as the Comparator or the ADC, refer to the appropriate section in this data sheet. 3.7.1.1 RE0/AN5/SEG21(1) 3.7.1.7 RE6/SEG26(2) Figure 3-28 shows the diagram for this pin.
PIC16F913/914/916/917/946 FIGURE 3-26: BLOCK DIAGRAM OF RE<2:0> (PIC16F914/917 AND PIC16F946 ONLY) VDD Data Bus WR PORTE D Q CK I/O Pin Q VSS Data Latch WR TRISE D Q CK Q TRIS Latch Analog Mode or SEG<23:21> and LCDEN Schmitt and LCDEN Trigger RD TRISE RD PORTE SEG<23:21> and LCDEN SEG<23:21> AN<7:5> FIGURE 3-27: BLOCK DIAGRAM OF RE3 MCLR circuit HV Schmitt Trigger Buffer MCLR Filter Programming mode HV Detect Input Pin MCLRE Data Bus RD TRISE VSS VSS HV Schmitt Trigger Buffer RD
PIC16F913/914/916/917/946 FIGURE 3-28: BLOCK DIAGRAM OF RE<7:4> (PIC16F946 ONLY) VDD Data Bus WR PORTE D Q CK I/O Pin Q VSS Data Latch WR TRISE D Q CK Q TRIS Latch Analog Mode or RD TRISE SEG<27:24> and LCDEN Schmitt Trigger RD PORTE SEG<27:24> SEG<27:24> and LCDEN AN<7:5> © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 TABLE 3-5: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on POR, BOR Value on all other Resets Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu LCDCON LCDSE2(1,2) L
PIC16F913/914/916/917/946 3.8 EXAMPLE 3-6: PORTF and TRISF Registers PORTF is an 8-bit port with Schmitt Trigger input buffers. RF<7:0> are individually configured as inputs or outputs, depending on the state of the port direction. The port bits are also multiplexed with LCD segment functions. PORTF is available on the PIC16F946 only.
PIC16F913/914/916/917/946 3.8.1 PIN DESCRIPTIONS AND DIAGRAMS Each PORTF pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. 3.8.1.1 RF0/SEG32 Figure 3-29 shows the diagram for this pin. The RF0 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.8.1.2 3.8.1.
PIC16F913/914/916/917/946 FIGURE 3-29: BLOCK DIAGRAM OF RF<7:0> VDD Data Bus D WR PORTF Q CK I/O Pin Q VSS Data Latch WR TRISF D Q CK Q TRIS Latch RD TRISF SE<35:28> and LCDEN Schmitt Trigger RD PORTF SE<35:28> and LCDEN SEG<35:28> TABLE 3-6: Name LCDCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTF(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 (1) SE31 SE
PIC16F913/914/916/917/946 3.9 EXAMPLE 3-7: PORTG and TRISG Registers PORTG is an 8-bit port with Schmitt Trigger input buffers. RG<5:0> are individually configured as inputs or outputs, depending on the state of the port direction. The port bits are also multiplexed with LCD segment functions. PORTG is available on the PIC16F946 only.
PIC16F913/914/916/917/946 3.9.1 PIN DESCRIPTIONS AND DIAGRAMS 3.9.1.4 Each PORTG pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individual functions, refer to the appropriate section in this data sheet. 3.9.1.1 Figure 3-30 shows the diagram for this pin. The RG0 pin is configurable to function as one of the following: • a general purpose I/O • an analog output for the LCD 3.9.1.
PIC16F913/914/916/917/946 SUMMARY OF REGISTERS ASSOCIATED WITH PORTG(1) TABLE 3-7: Name LCDCON Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets LMUX1 LMUX0 0001 0011 0001 0011 LCDEN SLPEN WERR VLCDEN CS1 CS0 LCDSE4(1) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 uuuu uuuu LCDSE5(1) — — — — — — SE41 SE40 ---- --00 ---- --uu PORTG(1) — — RG5 RG4 RG3 RG2 RG1 RG0 --xx xxxx --uu uuuu — — TRISG5 TRISG4 TRISG
PIC16F913/914/916/917/946 4.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 4.1 Overview The Oscillator module can be configured in one of eight clock modes. 1. 2. 3. The Oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 4-1 illustrates a block diagram of the Oscillator module. 4. 5.
PIC16F913/914/916/917/946 4.2 Oscillator Control The Oscillator Control (OSCCON) register (Figure 4-1) controls the system clock and frequency selection options.
PIC16F913/914/916/917/946 4.3 Clock Source Modes Clock Source modes can be classified as external or internal. External Clock Modes 4.4.1 OSCILLATOR START-UP TIMER (OST) If the Oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep.
PIC16F913/914/916/917/946 4.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 4-3). The mode selects a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.
PIC16F913/914/916/917/946 4.4.4 4.5 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. In RC mode, the RC circuit connects to OSC1. OSC2/CLKOUT outputs the RC oscillator frequency divided by 4.
PIC16F913/914/916/917/946 4.5.2.1 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 4-2). The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. REGISTER 4-2: When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred.
PIC16F913/914/916/917/946 4.5.3 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a postscaler and multiplexer (see Figure 4-1). Select 31 kHz, via software, using the IRCF<2:0> bits of the OSCCON register. See Section 4.5.4 “Frequency Select Bits (IRCF)” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM).
PIC16F913/914/916/917/946 FIGURE 4-6: HFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC Start-up Time 2-cycle Sync Running LFINTOSC ≠0 IRCF <2:0> =0 System Clock HFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC 2-cycle Sync Running LFINTOSC ≠0 IRCF <2:0> =0 System Clock LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Start-up Time 2-cycle Sync Running HFINTOSC IRCF <2:0> =0 ≠0 System Clock DS41250F-page 94 ©
PIC16F913/914/916/917/946 4.6 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bit of the OSCCON register. 4.6.1 SYSTEM CLOCK SELECT (SCS) BIT The System Clock Select (SCS) bit of the OSCCON register selects the system clock source that is used for the CPU and peripherals.
PIC16F913/914/916/917/946 4.7.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCCON register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word register (CONFIG), or the internal oscillator. FIGURE 4-7: TWO-SPEED START-UP HFINTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock DS41250F-page 96 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 4.8 Fail-Safe Clock Monitor 4.8.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Word register (CONFIG). The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO).
PIC16F913/914/916/917/946 FIGURE 4-9: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
PIC16F913/914/916/917/946 5.0 TIMER0 MODULE 5.1 Timer0 Operation The Timer0 module is an 8-bit timer/counter with the following features: When used as a timer, the Timer0 module can be used as either an 8-bit timer or an 8-bit counter. • • • • • 5.1.
PIC16F913/914/916/917/946 5.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit of the Option register. To assign the prescaler to Timer0, the PSA bit must be cleared to a ‘0’. There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256.
PIC16F913/914/916/917/946 REGISTER 5-1: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrup
PIC16F913/914/916/917/946 6.0 TIMER1 MODULE WITH GATE CONTROL 6.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.
PIC16F913/914/916/917/946 6.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of TCY as determined by the Timer1 prescaler. 6.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1 module may work as a timer or a counter. When counting, Timer1 is incremented on the rising edge of the external clock input T1CKI.
PIC16F913/914/916/917/946 6.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • Timer1 interrupt enable bit of the PIE1 register • PEIE bit of the INTCON register • GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.
PIC16F913/914/916/917/946 6.10 Timer1 Control Register The Timer1 Control register (T1CON), shown in Register 6-1, is used to control Timer1 and select the various features of the Timer1 module.
PIC16F913/914/916/917/946 TABLE 6-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets CMCON1 — — — — — — T1GSS C2SYNC ---- --10 ---- --10 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 uuuu uuuu TMR1H
PIC16F913/914/916/917/946 7.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’.
PIC16F913/914/916/917/946 REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler 0001 = 1:2 Postscaler 0010 = 1:3 Postscaler 0011 =
PIC16F913/914/916/917/946 8.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution.
PIC16F913/914/916/917/946 FIGURE 8-2: COMPARATOR C1 OUTPUT BLOCK DIAGRAM MULTIPLEX Port Pins C1INV To C1OUT pin C1 D Q1 To Data Bus Q EN RD CMCON0 Set C1IF bit D Q3*RD CMCON0 Q EN CL Reset Note 1: 2: FIGURE 8-3: Q1 and Q3 are phases of the four-phase system clock (FOSC). Q1 is held high during Sleep mode.
PIC16F913/914/916/917/946 8.1.1 ANALOG INPUT CONNECTION CONSIDERATIONS A simplified circuit for an analog input is shown in Figure 8-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC16F913/914/916/917/946 8.2 Comparator Configuration There are eight modes of operation for the comparator. The CM<2:0> bits of the CMCON0 register are used to select these modes as shown in Figure 8-5.
PIC16F913/914/916/917/946 FIGURE 8-5: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) CM<2:0> = 000 A VINC1INVIN+ C1IN+ A C2IN- Two Independent Comparators CM<2:0> = 100 VINC1IN- A Off (Read as ‘0’) C1 VIN- A VIN+ C2IN+ A C2INOff (Read as ‘0’) C2 Three Inputs Multiplexed to Two Comparators CM<2:0> = 001 C1INC1IN+ C2INC2IN+ A A CIS = 0 CIS = 1 VIN+ C1 C1OUT VIN+ A C1IN+ C2INC2IN+ A A A A CIS = 0 CIS = 1 C2 C2OUT VINVIN+ C1 C2 C2OUT From CVREF Module Two C
PIC16F913/914/916/917/946 8.3 Comparator Control 8.4 The CMCON0 register (Register 8-1) provides access to the following comparator features: • • • • Mode selection Output state Output polarity Input switch 8.3.1 COMPARATOR OUTPUT STATE Each comparator state can always be read internally via the associated CxOUT bit of the CMCON0 register. The comparator outputs are directed to the CxOUT pins when CM<2:0> = 110.
PIC16F913/914/916/917/946 FIGURE 8-6: COMPARATOR INTERRUPT TIMING W/O CMCON0 READ Q1 Q3 CIN+ TRT COUT Set CxIF (level) CxIF reset by software FIGURE 8-7: COMPARATOR INTERRUPT TIMING WITH CMCON0 READ Q1 Q3 CIN+ 8.6 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in the Section 19.0 “Electrical Specifications”.
PIC16F913/914/916/917/946 REGISTER 8-1: CMCON0: COMPARATOR CONFIGURATION REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparat
PIC16F913/914/916/917/946 8.8 Comparator C2 Gating Timer1 8.9 This feature can be used to time the duration or interval of analog events. Clearing the T1GSS bit of the CMCON1 register will enable Timer1 to increment based on the output of Comparator C2. This requires that Timer1 is on and gating is enabled. See Section 6.0 “Timer1 Module with Gate Control” for details.
PIC16F913/914/916/917/946 8.10 Comparator Voltage Reference EQUATION 8-1: The Comparator Voltage Reference module provides an internally generated voltage reference for the comparators.
PIC16F913/914/916/917/946 FIGURE 8-8: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16 Stages 8R R R R R VDD VRR 8R 16-1 Analog MUX VREN 15 14 CVREF to Comparator Input 2 1 0 VR<3:0>(1) VREN VR<3:0> = 0000 VRR Note 1: TABLE 8-2: Name Care should be taken to ensure VREF remains within the comparator common mode input range. See Section 19.0 “Electrical Specifications” for more detail.
PIC16F913/914/916/917/946 NOTES: DS41250F-page 120 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 9.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (AUSART) The AUSART module includes the following capabilities: • • • • • • • • • • The Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC16F913/914/916/917/946 FIGURE 9-2: AUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator +1 SPBRG RSR Register MSb Pin Buffer and Control Data Recovery FOSC Multiplier x4 x16 x64 SYNC 1 0 0 BRGH x 1 0 Stop OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the AUSART module is controlled through two registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) These
PIC16F913/914/916/917/946 9.1 AUSART Asynchronous Mode The AUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC16F913/914/916/917/946 9.1.1.4 TSR Status 9.1.1.6 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 9.1.1.
PIC16F913/914/916/917/946 TABLE 9-1: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 0000 0000 PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 000
PIC16F913/914/916/917/946 9.1.2 AUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 9-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC16F913/914/916/917/946 9.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG.
PIC16F913/914/916/917/946 9.1.2.8 1. 2. 3. 4. 5. 6. 7. 8. 9. Asynchronous Reception Set-up: 9.1.2.9 Initialize the SPBRG register and the BRGH bit to achieve the desired baud rate (see Section 9.2 “AUSART Baud Rate Generator (BRG)”). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit.
PIC16F913/914/916/917/946 TABLE 9-2: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 0000 0000 PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIC16F913/914/916/917/946 REGISTER 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN(1) SYNC — BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external
PIC16F913/914/916/917/946 REGISTER 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset
PIC16F913/914/916/917/946 9.2 AUSART Baud Rate Generator (BRG) EXAMPLE 9-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode: The Baud Rate Generator (BRG) is an 8-bit timer that is dedicated to the support of both the asynchronous and synchronous AUSART operation. F OS C Desired Baud Rate = --------------------------------------64 ( SPBRG + 1 ) The SPBRG register determines the period of the free running baud rate timer.
PIC16F913/914/916/917/946 TABLE 9-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0 BAUD RATE FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 1202 0.16 103 2400 2404 0.16 129 2400 0.
PIC16F913/914/916/917/946 TABLE 9-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 1 BAUD RATE FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 2.000 MHz FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 — 1202 — 0.16 — 103 300 1202 0.16 0.16 207 51 2400 2404 0.16 103 2400 0.00 95 2404 0.16 51 2404 0.
PIC16F913/914/916/917/946 9.3 AUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC16F913/914/916/917/946 FIGURE 9-6: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit ‘1’ ‘1’ Note: Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
PIC16F913/914/916/917/946 9.3.1.4 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the AUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register).
PIC16F913/914/916/917/946 FIGURE 9-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC16F913/914/916/917/946 9.3.2 SYNCHRONOUS SLAVE MODE If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: The following bits are used to configure the AUSART for Synchronous slave operation: • • • • • 1. SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation.
PIC16F913/914/916/917/946 9.3.2.3 AUSART Synchronous Slave Reception 9.3.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 9.3.1.4 “Synchronous Master Reception”), with the following exceptions: 1. 2. • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode 3. 4. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC16F913/914/916/917/946 9.4 AUSART Operation During Sleep The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 9.4.
PIC16F913/914/916/917/946 NOTES: DS41250F-page 142 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 10.0 LIQUID CRYSTAL DISPLAY (LCD) DRIVER MODULE The Liquid Crystal Display (LCD) driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16F913/916 devices, the module drives the panels of up to four commons and up to 16 segments. In the PIC16F914/917 devices, the module drives the panels of up to four commons and up to 24 segments. In the PIC16F946 device, the module drives the panels of up to four commons and up to 42 segments.
PIC16F913/914/916/917/946 FIGURE 10-1: LCD DRIVER MODULE BLOCK DIAGRAM Data Bus LCDDATAx Registers MUX SEG<41:0>(1, 2, 3) To I/O Pads(1) Timing Control LCDCON LCDPS COM<3:0>(3) To I/O Pads(1) LCDSEn FOSC/8192 T1OSC/32 LFINTOSC/32 Note 1: 2: 3: DS41250F-page 144 Clock Source Select and Prescaler These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module. SEG<23:0> on PIC16F914/917, SEG<15:0> on PIC16F913/916.
PIC16F913/914/916/917/946 REGISTER 10-1: LCDCON: LIQUID CRYSTAL DISPLAY CONTROL REGISTER R/W-0 R/W-0 R/C-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ C = Only clearable bit ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n = Value at POR bit 7 LCDEN: LCD Driver Enable bit 1 = LCD driver module is enabled 0 = LCD driver module is disabled bit 6 SLPEN:
PIC16F913/914/916/917/946 REGISTER 10-2: LCDPS: LCD PRESCALER SELECT REGISTER R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WFT: Waveform Type Select bit 1 = Type-B waveform (phase changes on each frame boundary) 0 = Type-A waveform (phase changes within each common interval) bit 6 BIASMD: Bias Mod
PIC16F913/914/916/917/946 REGISTER 10-3: LCDSEn: LCD SEGMENT ENABLE REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEn SEn SEn SEn SEn SEn SEn SEn bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown SEn: Segment Enable bits 1 = Segment function of the pin is enabled 0 = I/O function of the pin is enabled REGISTER 10-4: R/W-x LCDDATAx: LCD DATA REGIS
PIC16F913/914/916/917/946 10.2 LCD Clock Source Selection 10.2.1 The LCD driver module has 3 possible clock sources: • FOSC/8192 • T1OSC/32 • LFINTOSC/32 The first clock source is the system clock divided by 8192 (FOSC/8192). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz. The divider is not programmable. Instead, the LCD prescaler bits LP<3:0> of the LCDPS register are used to set the LCD frame clock rate.
PIC16F913/914/916/917/946 10.4 LCD Multiplex Types 10.7 The LCD driver module can be configured into one of four multiplex types: • • • • Static (only COM0 is used) 1/2 multiplex (COM<1:0> are used) 1/3 multiplex (COM<2:0> are used) 1/4 multiplex (COM<3:0> are used) On a Power-on Reset, the LMUX<1:0> bits of the LCDCON register are ‘11’. LMUX <1:0> RA3/RD0(1) RA2 Static 00 Digital I/O 1/2 01 Digital I/O 1/3 10 Digital I/O 1/4 11 Note 1: 10.
PIC16F913/914/916/917/946 FOSC LCD CLOCK GENERATION COM0 COM1 COM2 COM3 FIGURE 10-3: ÷8192 T1OSC 32 kHz Crystal Osc. LFINTOSC Nominal = 31 kHz ÷32 CS<1:0> (LCDCON<3:2>) DS41250F-page 150 ÷4 Static ÷2 1/2 ÷32 4-bit Prog Presc ÷1, 2, 3, 4 Ring Counter 1/3, 1/4 LP<3:0> (LCDPS<3:0>) LMUX<1:0> (LCDCON<1:0>) LMUX<1:0> (LCDCON<1:0>) © 2007 Microchip Technology Inc.
© 2007 Microchip Technology Inc.
DS41250F-page 152 COM0 LCDDATA12, 1 LCDDATA12, 2 LCDDATA12, 3 LCDDATA12, 4 LCDDATA12, 5 LCDDATA12, 6 LCDDATA12, 7 LCDDATA13, 0 LCDDATA13, 1 LCDDATA13, 2 LCDDATA13, 3 LCDDATA13, 4 LCDDATA13, 5 LCDDATA13, 6 LCDDATA13, 7 LCDDATA14, 0 LCDDATA14, 1 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 LCD Segment COM1 LCDDATA17, 1 LCDDATA17, 0 LCDDATA16, 7 LCDDATA16, 6 LCDDATA16, 5 LCDDATA16, 4 LCDDATA16, 3 LCDDATA16, 2
PIC16F913/914/916/917/946 10.8 LCD Waveform Generation LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero. The COM signal represents the time slice for each common, while the SEG contains the pixel data. The pixel signal (COM-SEG) will have no DC component and it can take only one of the two rms values.
PIC16F913/914/916/917/946 FIGURE 10-7: TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM1 V2 COM1 COM0 V1 V0 V2 V1 SEG0 V0 V2 V1 SEG1 V2 SEG1 SEG0 SEG2 SEG3 V0 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 1 Frame DS41250F-page 154 -V2 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-8: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE V2 V1 COM0 COM1 V0 COM0 V2 COM1 V1 V0 V2 SEG0 V1 SEG1 SEG0 SEG2 SEG3 V0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 2 Frames © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-9: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG1 SEG0 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 1 Frame DS41250F-page 156 -V2 -V3 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 COM1 V0 V3 COM0 V2 COM1 V1 V0 V3 V2 SEG0 V1 V0 SEG1 SEG0 SEG2 SEG3 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 2 Frames © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-11: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 V2 COM2 COM1 V1 V0 COM1 V2 COM0 COM2 V1 V0 V2 SEG0 SEG2 V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG1 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 1 Frame DS41250F-page 158 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-12: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE V2 COM0 V1 V0 COM2 V2 COM1 V1 COM1 V0 COM0 V2 COM2 V1 V0 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V2 SEG1 V1 V0 V2 V1 V0 COM0-SEG0 -V1 -V2 V2 V1 V0 COM0-SEG1 -V1 -V2 2 Frames © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 SEG2 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 1 Frame DS41250F-page 160 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE V3 V2 COM0 V1 V0 V3 COM2 V2 COM1 V1 COM1 V0 COM0 V3 V2 COM2 V1 V0 V3 V2 V1 V0 SEG0 SEG1 SEG2 SEG0 V3 V2 SEG1 V1 V0 V3 V2 V1 V0 COM0-SEG0 -V1 -V2 -V3 V3 V2 V1 V0 COM0-SEG1 -V1 -V2 -V3 2 Frames © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-15: TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 1 Frame DS41250F-page 162 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 10-16: TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE COM3 COM2 COM1 COM0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 COM3 V3 V2 V1 V0 SEG0 V3 V2 V1 V0 SEG1 V3 V2 V1 V0 COM0-SEG0 V3 V2 V1 V0 -V1 -V2 -V3 COM0-SEG1 V3 V2 V1 V0 -V1 -V2 -V3 SEG0 SEG1 COM0 2 Frames © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 10.9 LCD Interrupts component would be introduced into the panel. Therefore, when using Type-B waveforms, the user must synchronize the LCD pixel updates to occur within a subframe after the frame interrupt. The LCD timing generation provides an interrupt that defines the LCD frame timing. A new frame is defined to begin at the leading edge of the COM0 common signal.
PIC16F913/914/916/917/946 10.10 Operation During Sleep The LCD module can operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep. If a SLEEP instruction is executed and SLPEN = 1, the LCD module will cease all functions and go into a very low-current Consumption mode.
PIC16F913/914/916/917/946 FIGURE 10-18: SLEEP ENTRY/EXIT WHEN SLPEN = 1 V3 V2 V1 COM0 V0 V3 V2 V1 V0 COM1 V3 V2 V1 V0 COM2 V3 V2 V1 V0 SEG0 2 Frames SLEEP Instruction Execution DS41250F-page 166 Wake-up © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 10.11 Configuring the LCD Module 10.13 LCD Current Consumption The following is the sequence of steps to configure the LCD module. When using the LCD module the current consumption consists of the following three factors: 1. 1. 2. 3. 2. 3. 4. 5. 6. 7. Select the frame clock prescale using bits LP<3:0> of the LCDPS register. Configure the appropriate pins to function as segment drivers using the LCDSEn registers.
PIC16F913/914/916/917/946 TABLE 10-6: Name CMCON0 REGISTERS ASSOCIATED WITH LCD OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000 INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011 LCDDATA0 SEG7 COM0 SEG6 COM0 SEG5 COM0 SEG4 COM0 SEG3 COM0 SEG2 COM0 SEG1 COM0 SEG
PIC16F913/914/916/917/946 TABLE 10-6: REGISTERS ASSOCIATED WITH LCD OPERATION (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets LCDSE2(2) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu LCDSE3(3) SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 0000 0000 LCDSE4(3) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 0000 0000 LCDSE5(3) — — — — — — SE41 SE40 ---- --00 ---- --00 PIE2
PIC16F913/914/916/917/946 NOTES: DS41250F-page 170 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 11.0 PROGRAMMABLE LOW-VOLTAGE DETECT (PLVD) MODULE The Programmable Low-Voltage Detect (PLVD) module is a power supply detector which monitors the internal power supply. This module is typically used in key fobs and other devices, where certain actions need to be taken as a result of a falling battery voltage.
PIC16F913/914/916/917/946 11.1 PLVD Operation To setup the PLVD for operation, the following steps must be taken: • Enable the module by setting the LVDEN bit of the LVDCON register. • Configure the trip point by setting the LVDL<2:0> bits of the LVDCON register. • Wait for the reference voltage to become stable. Refer to Section 11.4 “Stable Reference Indication”. • Clear the LVDIF bit of the PIR2 register. The LVDIF bit will be set when VDD falls below the PLVD trip point.
PIC16F913/914/916/917/946 REGISTER 11-1: U-0 LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER U-0 — R-0 (1) — IRVST R/W-0 U-0 R/W-1 R/W-0 R/W-0 LVDEN — LVDL2 LVDL1 LVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Status Flag bit(1) 1 = Indicates that the PLVD is stable and PLVD interru
PIC16F913/914/916/917/946 NOTES: DS41250F-page 174 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 12.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC voltage reference is software selectable to be either internally generated or externally supplied. The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal.
PIC16F913/914/916/917/946 12.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 12.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits.
PIC16F913/914/916/917/946 TABLE 12-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V) ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS<2:0> 20 MHz 8 MHz (2) 2.0 μs 1.0 μs(2) 4.0 μs 2.0 μs 8.0 μs(3) 2.0 μs 4.0 μs 16.0 μs(3) 4.0 μs 8.0 μs(3) 32.0 μs(3) FOSC/2 000 100 ns 100 200 ns(2) 500 ns(2) 001 400 ns (2) (2) 800 ns (2) FOSC/16 101 FOSC/32 010 500 ns 1.0 μs (3) FOSC/64 110 3.
PIC16F913/914/916/917/946 12.1.6 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON0 register controls the output format. Figure 12-4 shows the two output formats. FIGURE 12-3: 10-BIT A/D CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit A/D Result Unimplemented: Read as ‘0’ MSB (ADFM = 1) bit 7 LSB bit 0 Unimplemented: Read as ‘0’ 12.2 12.2.
PIC16F913/914/916/917/946 12.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC16F913/914/916/917/946 REGISTER 12-1: ADCON0: A/D CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 VCFG1: Voltage Reference bit 1 = VREF- pin 0 = VSS bit
PIC16F913/914/916/917/946 REGISTER 12-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — ADCS2 ADCS1 ADCS0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from a dedicated internal osci
PIC16F913/914/916/917/946 REGISTER 12-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 12-4: ADRESL: ADC RESULT RE
PIC16F913/914/916/917/946 12.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 12-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-4.
PIC16F913/914/916/917/946 FIGURE 12-4: ANALOG INPUT MODEL VDD Rs VA VT = 0.6V ANx CPIN 5 pF Sampling Switch SS Rss RIC ≤ 1k I LEAKAGE(1) VT = 0.6V CHOLD = 10 pF VSS/VREF- 6V 5V VDD 4V 3V 2V Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: FIGURE 12-5: RSS 5 6 7 8 9 10 11 Sampling Switch (kΩ) See Section 19.
PIC16F913/914/916/917/946 TABLE 12-2: Name SUMMARY OF ASSOCIATED ADC REGISTERS Bit 7 Bit 6 Bit 5 ADCON0 ADFM VCFG1 ADCON1 — ADCS2 ANS7 ANS6 ANSEL Value on POR, BOR Value on all other Resets Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000 ADCS1 ADCS0 — — — — -000 ---- -000 ---- ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111 ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu ADRESL A/D Result Register Low Byte xxxx
PIC16F913/914/916/917/946 NOTES: DS41250F-page 186 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 13.0 DATA EEPROM AND FLASH PROGRAM MEMORY CONTROL Data EEPROM memory is readable and writable and the Flash program memory is readable during normal operation (full VDD range). These memories are not directly mapped in the register file space. Instead, they are indirectly addressed through the Special Function Registers.
PIC16F913/914/916/917/946 REGISTER 13-1: EEDATL: EEPROM/PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown EEDATL<7:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory REGISTER
PIC16F913/914/916/917/946 REGISTER 13-5: EECON1: EEPROM CONTROL REGISTER R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 Legend: S = Bit can only be set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory bit 6-4 Unimplemented: Read as ‘0’ bit 3 WRERR: EEP
PIC16F913/914/916/917/946 13.1.2 READING THE DATA EEPROM MEMORY To read a data memory location, the user must write the address to the EEADRL register, clear the EEPGD control bit, and then set control bit RD of the EECON1 register. The data is available in the very next cycle, in the EEDATL register; therefore, it can be read in the next instruction. EEDATL will hold this value until another read or until it is written to by the user (during a write operation).
PIC16F913/914/916/917/946 13.1.4 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must write two bytes of the address to the EEADRL and EEADRH registers, set the EEPGD control bit, and then set control bit RD of the EECON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored.
PIC16F913/914/916/917/946 FIGURE 13-1: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR PC + 1 Flash Data INSTR (PC) INSTR(PC - 1) executed here EEADRH,EEADRL INSTR (PC + 1) BSF EECON1,RD executed here PPC+3 C+3 EEDATH,EEDATL INSTR(PC + 1) executed here PC + 5 PC + 4 INSTR (PC + 3) Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit EEDATH EEDATL register
PIC16F913/914/916/917/946 14.0 SSP MODULE OVERVIEW FIGURE 14-1: The Synchronous Serial Port (SSP) module is a serial interface used to communicate with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F913/914/916/917/946 REGISTER 14-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire)
PIC16F913/914/916/917/946 REGISTER 14-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3(2) SSPM2(2) SSPM1(2) SSPM0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be
PIC16F913/914/916/917/946 14.2 Operation When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>).
PIC16F913/914/916/917/946 14.3 Enabling SPI I/O 14.4 To enable the serial port, SSP Enable bit SSPEN of the SSPCON register must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC16F913/914/916/917/946 14.5 Master Mode The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 14-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC16F913/914/916/917/946 14.6 Slave Mode In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data.
PIC16F913/914/916/917/946 FIGURE 14-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 14-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit
PIC16F913/914/916/917/946 14.8 Sleep Operation 14.10 Bus Mode Compatibility In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to Normal mode, the module will continue to transmit/receive data. Table 14-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits.
PIC16F913/914/916/917/946 14.11 SSP I2C Operation The SSP module in I2C mode, fully implements all slave functions, except general call support, and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the Standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer.
PIC16F913/914/916/917/946 14.12.1 ADDRESSING Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of register SSPADD <7:1>. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16F913/914/916/917/946 14.12.2 RECEPTION When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF of the SSPSTAT register is set, or bit SSPOV of the SSPCON register is set. This is an error condition due to the user’s firmware.
© 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 14.12.3 TRANSMISSION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register.
© 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 14.13 Master Mode 14.14 Multi-Master Mode Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I2C bus may be taken when the P bit is set or the bus is idle and both the S and P bits are clear.
PIC16F913/914/916/917/946 FIGURE 14-12: CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX-1 SCL Master device asserts clock CKP Master device deasserts clock WR SSPCON TABLE 14-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x LCDCON LCDE
PIC16F913/914/916/917/946 NOTES: DS41250F-page 210 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 15.0 CAPTURE/COMPARE/PWM (CCP) MODULE TABLE 15-1: The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate a Pulse-Width Modulated signal of varying frequency and duty cycle.
PIC16F913/914/916/917/946 REGISTER 15-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCP1M3 CCP1M2 CCP1M1 CCP1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two
PIC16F913/914/916/917/946 15.1 Capture Mode 15.1.2 In Capture mode, CCPRxH:CCPRxL captures the 16-bit value of the TMR1 register when an event occurs on pin CCPx. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software.
PIC16F913/914/916/917/946 15.2 Compare Mode 15.2.2 In Compare mode, the 16-bit CCPRx register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCPx module may: • • • • • Toggle the CCPx output. Set the CCPx output. Clear the CCPx output. Generate a Special Event Trigger. Generate a Software Interrupt. All Compare modes can generate an interrupt.
PIC16F913/914/916/917/946 15.3 PWM Mode The PWM mode generates a Pulse-Width Modulated signal on the CCPx pin. The duty cycle, period and resolution are determined by the following registers: • • • • PR2 T2CON CCPRxL CCPxCON FIGURE 15-4: CCP PWM OUTPUT Period Pulse Width In Pulse-Width Modulation (PWM) mode, the CCP module produces up to a 10-bit resolution PWM output on the CCPx pin.
PIC16F913/914/916/917/946 15.3.1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 15-1. EQUATION 15-1: (TMR2 Prescale Value) TOSC = 1/FOSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: 15.3.
PIC16F913/914/916/917/946 15.3.3 PWM RESOLUTION EQUATION 15-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 15-4.
PIC16F913/914/916/917/946 15.3.4 OPERATION IN SLEEP MODE 15.3.7 In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 15.3.5 The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency.
PIC16F913/914/916/917/946 16.0 SPECIAL FEATURES OF THE CPU The PIC16F91X/946 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving features and offer code protection.
PIC16F913/914/916/917/946 16.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’) to select various device configurations as shown in Register 16-1. These bits are mapped in program memory location 2007h. REGISTER 16-1: — Note: Address 2007h is beyond the user program memory space. It belongs to the special configuration memory space (2000h-3FFFh), which can be accessed only during programming.
PIC16F913/914/916/917/946 16.2 Resets The PIC16F91X/946 differentiates between various kinds of Reset: a) b) c) d) e) f) Power-on Reset (POR) WDT Reset during normal operation WDT Reset during Sleep MCLR Reset during normal operation MCLR Reset during Sleep Brown-out Reset (BOR) Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset.
PIC16F913/914/916/917/946 16.2.1 POWER-ON RESET (POR) FIGURE 16-2: The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. A maximum rise time for VDD is required. See Section 19.0 “Electrical Specifications” for details.
PIC16F913/914/916/917/946 16.2.4 BROWN-OUT RESET (BOR) If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be re-initialized. Once VDD rises above VBOR, the Power-up Timer will execute a 64 ms Reset. The BOREN0 and BOREN1 bits in the Configuration Word register selects one of four BOR modes. Two modes have been added to allow software or hardware control of the BOR enable.
PIC16F913/914/916/917/946 16.2.6 TIME-OUT SEQUENCE 16.2.7 On power-up, the time-out sequence is as follows: first, PWRT time-out is invoked after POR has expired, then OST is activated after the PWRT time-out has expired. The total time-out will vary based on oscillator configuration and PWRTE bit status. For example, in EC mode with PWRTE bit erased (PWRT disabled), there will be no time-out at all. Figure 16-4, Figure 16-5 and Figure 16-6 depict time-out sequences.
PIC16F913/914/916/917/946 FIGURE 16-4: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 FIGURE 16-5: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 16-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 TABLE 16-4: Register INITIALIZATION CONDITION FOR REGISTERS Address Power-on Reset W • MCLR Reset • WDT Reset • Brown-out Reset(1) • Wake-up from Sleep through interrupt • Wake-up from Sleep through WDT time-out — xxxx xxxx uuuu uuuu uuuu uuuu INDF 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu TMR0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h/82h/ 102h/182h 0000 0000 0000 0000 PC + 1(3) STATUS 03h/83h/ 103h/183h 0001 1xxx 000q quuu(4) uuuq quuu(4)
PIC16F913/914/916/917/946 TABLE 16-4: Register INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) • MCLR Reset • WDT Reset • Brown-out Reset(1) • Wake-up from Sleep through interrupt • Wake-up from Sleep through WDT time-out Address Power-on Reset RCREG 1Ah 0000 0000 0000 0000 uuuu uuuu CCPR2L(6) 1Bh xxxx xxxx xxxx xxxx uuuu uuuu CCPR2H(6) 1Ch xxxx xxxx xxxx xxxx uuuu uuuu CCP2CON(6) 1Dh --00 0000 --00 0000 --uu uuuu ADRESH 1Eh xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1Fh 0000 00
PIC16F913/914/916/917/946 TABLE 16-4: Register INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) • MCLR Reset • WDT Reset • Brown-out Reset(1) • Wake-up from Sleep through interrupt • Wake-up from Sleep through WDT time-out Address Power-on Reset LVDCON 109h --00 -100 --00 -100 --uu -uuu EEDATL 10Ch 0000 0000 0000 0000 uuuu uuuu EEADRL 10Dh 0000 0000 0000 0000 uuuu uuuu EEDATH 10Eh --00 0000 0000 0000 uuuu uuuu EEADRH 10Fh ---0 0000 0000 0000 uuuu uuuu LCDDATA0 110h xxxx xxx
PIC16F913/914/916/917/946 TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) • Wake-up from Sleep through interrupt • Wake-up from Sleep through WDT time-out • MCLR Reset • WDT Reset • Brown-out Reset(1) Register Address Power-on Reset LCDDATA22(7) 19Ah xxxx xxxx uuuu uuuu uuuu uuuu LCDDATA23(7) 19Bh ---- --xx ---- --uu ---- --uu LCDSE3(7) 19Ch 0000 0000 uuuu uuuu uuuu uuuu LCDSE4(7) 19Dh 0000 0000 uuuu uuuu uuuu uuuu (7) 19Eh ---- --00 ---- --uu ---- --uu 18Ch x-
PIC16F913/914/916/917/946 16.
PIC16F913/914/916/917/946 16.3.1 RB0/INT/SEG0 INTERRUPT 16.3.2 External interrupt on RB0/INT/SEG0 pin is edge-triggered; either rising if the INTEDG bit of the OPTION register is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT/SEG0 pin, the INTF bit of the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit of the INTCON register.
PIC16F913/914/916/917/946 FIGURE 16-8: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(3) (4) INT pin (1) (1) INTF Flag (INTCON reg.) Interrupt Latency (2) (5) GIE bit (INTCON reg.
PIC16F913/914/916/917/946 16.3.4 CONTEXT SAVING DURING INTERRUPTS During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Since the lower 16 bytes of all banks are common in the PIC16F91X/946 (see Figure 2-3), temporary holding registers, W_TEMP and STATUS_TEMP, should be placed in here.
PIC16F913/914/916/917/946 16.4 Watchdog Timer (WDT) For PIC16F91X/946, the WDT has been modified from previous PIC16F devices. The new WDT is code and functionally compatible with previous PIC16F WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to have a scaled value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds. WDT is cleared under certain conditions described in Table 16-7.
PIC16F913/914/916/917/946 REGISTER 16-2: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 105h) U-0 U-0 U-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN bit 7 bit 0 bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (Reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100
PIC16F913/914/916/917/946 16.5 Power-Down Mode (Sleep) The Power-down mode is entered by executing a SLEEP instruction. If the Watchdog Timer is enabled: • • • • • • WDT will be cleared but keeps running. PD bit in the STATUS register is cleared. TO bit is set. Oscillator driver is turned off. Timer1 oscillator is unaffected I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance).
PIC16F913/914/916/917/946 Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
PIC16F913/914/916/917/946 16.6 Code Protection FIGURE 16-11: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION If the code protection bit(s) have not been programmed, the on-chip program memory can be read out using ICSP for verification purposes. Note: The entire data EEPROM and Flash program memory will be erased when the code protection is turned off. See the “PIC16F91X/946 Memory Programming Specification” (DS41244) for more information.
PIC16F913/914/916/917/946 16.9 In-Circuit Debugger 16.9.1 When the debug bit in the Configuration Word register is programmed to a ‘0’, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB® ICD 2. When the microcontroller has this feature enabled, some of the resources are not available for general use. See Table 16-9 for more detail. Note: The user’s application must have the circuitry required to support ICD functionality.
PIC16F913/914/916/917/946 NOTES: DS41250F-page 240 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 17.
PIC16F913/914/916/917/946 TABLE 17-2: PIC16F913/914/916/917/946 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0
PIC16F913/914/916/917/946 17.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW BCF k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register.
PIC16F913/914/916/917/946 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: None Operation: Operation: skip if (f) = 1 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction.
PIC16F913/914/916/917/946 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16F913/914/916/917/946 MOVWF Move W to f Syntax: [ label ] MOVF Move f Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Operation: (f) → (dest) Status Affected: None Status Affected: Z Description: Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself.
PIC16F913/914/916/917/946 RETFIE Return from Interrupt RETLW Return with literal in W Syntax: [ label ] Syntax: [ label ] RETFIE RETLW k Operands: None Operands: 0 ≤ k ≤ 255 Operation: TOS → PC, 1 → GIE Operation: k → (W); TOS → PC Status Affected: None Status Affected: None Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two-cycle instruction.
PIC16F913/914/916/917/946 RLF Rotate Left f through Carry SLEEP Enter Sleep mode Syntax: [ label ] Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16F913/914/916/917/946 SUBWF Subtract W from f XORLW Exclusive OR literal with W Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 255 Operation: (f) - (W) → (destination) Status Affected: C, DC, Z Description: SWAPF Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of the W register are XOR’ed with the eight-bit literal ‘k’. The result is placed in the W register.
PIC16F913/914/916/917/946 NOTES: DS41250F-page 250 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 18.
PIC16F913/914/916/917/946 18.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.
PIC16F913/914/916/917/946 18.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F913/914/916/917/946 18.11 PICSTART Plus Development Programmer 18.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins.
PIC16F913/914/916/917/946 19.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings(†) Ambient temperature under bias..........................................................................................................-40° to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on VDD with respect to VSS ..................................................................................
PIC16F913/914/916/917/946 FIGURE 19-1: PIC16F913/914/916/917/946 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C 5.5 5.0 VDD (V) 4.5 4.0 3.5 3.0 2.5 2.0 0 8 10 20 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE FIGURE 19-2: 125 ± 5% Temperature (°C) 85 ± 2% 60 ± 1% 25 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41250F-page 256 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 19.1 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) PIC16F913/914/916/917/946-E (Extended) DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Min. Typ† Max. Units Sym. Characteristic Conditions VDD Supply Voltage 2.0 2.0 3.0 4.5 — — — — 5.5 5.5 5.5 5.
PIC16F913/914/916/917/946 19.2 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) PIC16F913/914/916/917/946-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. D010 Device Characteristics Supply Current (IDD) D011* D012 D013* D014 D015 D016* D017 D018 D019 (1, 2) Conditions Min. Typ† Max. Units — 13 19 μA 2.0 — 22 30 μA 3.
PIC16F913/914/916/917/946 19.3 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) DC CHARACTERISTICS Param No. D020 Device Characteristics Power-down Base Current(IPD)(2) D021 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Min. Typ† Max. Units — 0.05 1.2 — 0.15 1.5 Conditions VDD Note μA 2.0 μA 3.0 WDT, BOR, Comparators, VREF and T1OSC disabled — 0.35 1.8 μA 5.0 — 150 500 nA 3.
PIC16F913/914/916/917/946 19.4 DC Characteristics: PIC16F913/914/916/917/946-E (Extended) DC CHARACTERISTICS Param No. D020E Device Characteristics Power-down Base Current (IPD)(2) D021E Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C for extended Min. Typ† Max. Units — 0.05 9 μA Conditions VDD Note 2.0 WDT, BOR, Comparators, VREF and T1OSC disabled — 0.15 11 μA 3.0 — 0.35 15 μA 5.0 — 1 28 μA 2.0 — 2 30 μA 3.
PIC16F913/914/916/917/946 19.5 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) PIC16F913/914/916/917/946-E (Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended DC CHARACTERISTICS Param No. Sym. VIL Characteristic Min. Typ† Max. Units Vss Vss Conditions — 0.8 V 4.5V ≤ VDD ≤ 5.5V — 0.15 VDD V 2.0V ≤ VDD ≤ 4.5V Vss — 0.2 VDD V 2.0V ≤ VDD ≤ 5.
PIC16F913/914/916/917/946 19.5 DC Characteristics: PIC16F913/914/916/917/946-I (Industrial) PIC16F913/914/916/917/946-E (Extended) (Continued) DC CHARACTERISTICS Param No. Sym. Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Min. Typ† Max.
PIC16F913/914/916/917/946 19.6 Thermal Considerations Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. TH01 TH02 TH03 TH04 TH05 TH06 TH07 Note 1: 2: 3: Symbol θJA Characteristic Thermal Resistance Junction to Ambient Typ. Units 60.0 80.0 90.0 27.5 47.2 46.0 24.4 77.0 31.4 24.0 24.0 20.0 24.7 14.5 20.0 24.
PIC16F913/914/916/917/946 19.7 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC16F913/914/916/917/946 19.8 AC Characteristics: PIC16F913/914/916/917/946 (Industrial, Extended) FIGURE 19-4: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP, XT, HS Modes) OSC2/CLKOUT (CLKOUT Mode) TABLE 19-1: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. OS01 Sym.
PIC16F913/914/916/917/946 TABLE 19-2: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units Conditions OS06 TWARM Internal Oscillator Switch when running(3) — — — 2 TOSC Slowest clock OS07 TSC Fail-Safe Sample Clock Period(1) — — 21 — ms LFINTOSC/64 OS08 HFOSC Internal Calibrated HFINTOSC Frequency(2) ±1% 7.92 8.0 8.08 MHz VDD = 3.
PIC16F913/914/916/917/946 FIGURE 19-5: CLKOUT AND I/O TIMING Cycle Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 19-3: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Symbol Characteristic Min. Typ† Max.
PIC16F913/914/916/917/946 FIGURE 19-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low.
PIC16F913/914/916/917/946 TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param Symbol No. Characteristic Min. Typ† Max.
PIC16F913/914/916/917/946 FIGURE 19-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No.
PIC16F913/914/916/917/946 TABLE 19-6: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param No. Symbol Characteristics CM01 VOS Input Offset Voltage CM02 VCM Input Common Mode Voltage CM03* CMRR Common Mode Rejection Ratio CM04* TRT Response Time Min. Typ† Max. Units — ± 5.0 ± 10 mV 0 — VDD – 1.
PIC16F913/914/916/917/946 TABLE 19-8: PIC16F913/914/916/917/946 A/D CONVERTER (ADC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 bits AD02 EIL Integral Error — — ±1 LSb VREF = 5.12V AD03 EDL Differential Error — — ±1 LSb No missing codes to 10 bits VREF = 5.12V AD04 EOFF Offset Error — — ±1 LSb VREF = 5.
PIC16F913/914/916/917/946 TABLE 19-9: PIC16F913/914/916/917/946 A/D CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param Sym. No. AD130* TAD Characteristic A/D Clock Period A/D Internal RC Oscillator Period AD131 TCNV Conversion Time (not including Acquisition Time)(1) Min. Typ† 1.6 — 9.0 μs TOSC-based, VREF ≥ 3.0V 3.0 — 9.0 μs TOSC-based, VREF full range 3.0 6.0 9.0 μs ADCS<1:0> = 11 (ADRC mode) At VDD = 2.
PIC16F913/914/916/917/946 FIGURE 19-9: PIC16F913/914/916/917/946 A/D CONVERSION TIMING (NORMAL MODE) BSF ADCON0, GO 1 TCY (TOSC/2(1)) AD134 AD131 Q4 AD130 A/D CLK 9 A/D Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO DONE Note 1: Sampling Stopped AD132 Sample If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
PIC16F913/914/916/917/946 FIGURE 19-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK SCK/SCL/SEG9 121 121 RC7/RX/DT/ SDI/SDA/SEG8 120 Note: 122 Refer to Figure 19-3 for load conditions. TABLE 19-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C ≤ TA ≤ +125°C Param. No. 120 121 122 Symbol Characteristic Min. Max. Units TCKH2DT V SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.
PIC16F913/914/916/917/946 FIGURE 19-13: CAPTURE/COMPARE/PWM TIMINGS CCP1/CCP2 (Capture mode) 50 51 52 CCP1/CCP2 (Compare mode) 53 54 Note: Refer to Figure 19-3 for load conditions. TABLE 19-12: CAPTURE/COMPARE/PWM (CCP) REQUIREMENTS Param. Sym. Characteristic No. 50* TCCL CCPx input low time Min. No Prescaler With Prescaler 3.0-5.5V 2.0-5.5V 51* TCCH CCPx input high time No Prescaler With Prescaler 3.0-5.5V 2.0-5.5V Typ† Max. Units Conditions 0.
PIC16F913/914/916/917/946 TABLE 19-13: PIC16F913/914/916/917/946 PLVD CHARACTERISTICS: DC CHARACTERISTICS Sym. VPLVD Min. Typ† Max. (85°C) Max. (125°C) Units LVDL<2:0> = 001 1.900 2.0 2.100 2.125 V LVDL<2:0> = 010 2.000 2.1 2.200 2.225 V LVDL<2:0> = 011 2.100 2.2 2.300 2.325 V LVDL<2:0> = 100 2.200 2.3 2.400 2.425 V LVDL<2:0> = 101 3.825 4.0 4.175 4.200 V LVDL<2:0> = 110 4.025 4.2 4.375 4.400 V LVDL<2:0> = 111 4.425 4.5 4.675 4.
PIC16F913/914/916/917/946 FIGURE 19-14: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 19-3 for load conditions.
PIC16F913/914/916/917/946 FIGURE 19-16: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb bit 6 - - - - - -1 77 75, 76 SDI MSb In bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 19-3 for load conditions. FIGURE 19-17: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 bit 6 - - - -1 LSb In 74 Note: Refer to Figure 19-3 for load conditions.
PIC16F913/914/916/917/946 TABLE 19-14: SPI MODE REQUIREMENTS Param No. Symbol Characteristic TSSL2SCH, SS↓ to SCK↓ or SCK↑ input TSSL2SCL 70* Min. Typ† Max.
PIC16F913/914/916/917/946 TABLE 19-15: I2C™ BUS START/STOP BITS REQUIREMENTS Param No. Symbol 90* TSU:STA Start condition Setup time 400 kHz mode 600 — — ns Only relevant for Repeated Start condition 91* THD:STA Start condition Hold time 400 kHz mode 600 — — ns After this period, the first clock pulse is generated 92* TSU:STO Stop condition Setup time 400 kHz mode 600 — — ns 93 THD:STO Stop condition Hold time 400 kHz mode 600 — — ns * Characteristic Min. Typ. Max.
PIC16F913/914/916/917/946 TABLE 19-16: I2C™ BUS DATA REQUIREMENTS Param. No. 100* Symbol THIGH Characteristic Clock high time 400 kHz mode SSP Module 101* TLOW Clock low time 400 kHz mode SSP Module Min. Max. Units 0.6 — μs 1.5TCY — Device must operate at a minimum of 10 MHz μs Device must operate at a minimum of 10 MHz 1.3 — 1.5TCY — Conditions 102* TR SDA and SCL rise time 400 kHz mode 20 + 0.
PIC16F913/914/916/917/946 20.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC16F913/914/916/917/946 FIGURE 20-2: MAXIMUM IDD vs. FOSC OVER VDD (EC MODE) 6.0 5.0 5.5V Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5V 4.0 IDD (mA) 4V 3.0 3V 2.0 2V 1.0 0.0 1 MHz 2 MHz 4 MHz 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz VDD (V) FIGURE 20-3: TYPICAL IDD vs. FOSC OVER VDD (HS MODE) HS Mode 5.0 4.5 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5.5V 5V 4.5V IDD (mA) 3.
PIC16F913/914/916/917/946 FIGURE 20-4: MAXIMUM IDD vs. FOSC OVER VDD (HS MODE) HS Mode 5.5 5.0 4.5 4.0 5.5V 5V 4.5V Typical: Mean @25°C4V 3V Statistical 3.5V 4.5V 5V 5.5V Maximum: Mean (Worst-case Temp) + 3σ 0.8868608641.0693043161.2645617521.4868166111.5076394231.520959608 (-40°C1.6176371031.9623642592.3355493582.7630868222.8139211682.849632041 to 125°C) 3.8375797553.9157601913.967889512 4.685048474 4.78069621 IDD (mA) 3.5 3.0 2.5 4V 2.0 3.5V 3V 1.5 1.0 0.5 0.
PIC16F913/914/916/917/946 FIGURE 20-6: MAXIMUM IDD vs. VDD OVER FOSC (XT MODE) XT Mode 1,800 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,600 1,400 IDD (uA) 1,200 1,000 4 MHz 800 600 1 MHz 400 200 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.5 5.0 5.5 VDD (V) TYPICAL IDD vs.
PIC16F913/914/916/917/946 FIGURE 20-8: MAXIMUM IDD vs. VDD (EXTRC MODE) 2,000 Typical: Typical:Statistical StatisticalMean Mean@25°C @25×C Maximum:Mean Mean(Worst-case (Worst CaseTemp) Temp)+ +3σ3 Maximum: (-40×C to 125×C) (-40°C to 125°C) 1,800 1,600 1,400 4 Mhz IDD (uA) 1,200 1,000 800 1 Mhz 600 400 200 0 2.0 2.5 3.0 4.0 3.5 4.5 5.0 5.5 VDD (V) FIGURE 20-9: IDD vs.
PIC16F913/914/916/917/946 FIGURE 20-10: IDD vs. VDD (LP MODE) 80 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 70 IDD (uA) 60 50 32 kHz Maximum 40 30 32 kHz Typical 20 10 0 2.0 3.0 2.5 4.0 3.5 4.5 5.0 5.5 VDD (V) FIGURE 20-11: TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE) 4V 2,500 IDD (uA) 2,000 HFINTOSC 5V 5.5V 197.9192604299.82617395.019 496.999 574.901 210.9124688 324.4079 431.721 544.182 620.
PIC16F913/914/916/917/946 FIGURE 20-12: MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE) HFINTOSC 3,000 2,500 5.5V Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 5V IDD (uA) 2,000 4V 1,500 3V 1,000 2V 500 0 125 kHz 250 kHz 500 kHz 1 MHz 2 MHz 4 MHz 8 MHz VDD (V) FIGURE 20-13: TYPICAL IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Typical (Sleep Mode all Peripherals Disabled) 0.45 0.
PIC16F913/914/916/917/946 FIGURE 20-14: MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) Maximum (Sleep Mode all Peripherals Disabled) 18 16 Typical: Statistical Mean @25°C Maximum: Mean + 3σ Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 14 Max. 125°C IPD (μA) 12 10 8 6 4 Max. 85°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-15: COMPARATOR IPD vs.
PIC16F913/914/916/917/946 FIGURE 20-16: BOR IPD vs. VDD OVER TEMPERATURE 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 140 IPD (uA) 120 100 80 60 40 Maximum 2.5 3 3.5 4 4.5 5 5.5 Typical 35.0 44.4 56.2 68.1 79.9 91.7 104.1 Max 51.1 65.0 82.5 100.0 117.5 135.1 Typical 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-17: TYPICAL WDT IPD vs. VDD (25°C) 3.0 2.5 IPD (uA) 2.0 1.
PIC16F913/914/916/917/946 FIGURE 20-18: MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE 40.0 35.0 Maximum: Mean +3 Maximum: Mean + 3σ Max. 125°C 30.0 IPD (uA) 25.0 20.0 15.0 10.0 Max. 85°C 5.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-19: WDT PERIOD vs. VDD OVER TEMPERATURE WDT Time-out Period 32 30 Maximum: Mean + 3σ (-40°C to 125°C) 28 Max. (125°C) 26 Max. (85°C) Time (ms) 24 22 20 Typical 18 16 14 Minimum 12 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F913/914/916/917/946 FIGURE 20-20: WDT PERIOD vs. TEMPERATURE (VDD = 5.0V) Vdd = 5V 30 28 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 26 Maximum Time (ms) 24 22 20 Typical 18 16 Minimum 14 12 10 -40°C 25°C 85°C 125°C Temperature (°C) FIGURE 20-21: CVREF IPD vs. VDD OVER TEMPERATURE (HIGH RANGE) High Range IPD (uA) 140 Max 85×C Max 125×C 35.8 68.0 Mean @25°C Typical: Statistical 44.8 77.3 (Worst-case Temp) + 3σ Maximum: Mean 53.8 86.5 120 (-40°C to 125°C) 62.
PIC16F913/914/916/917/946 FIGURE 20-22: CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE) low Range 180 160 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 140 Max. 125°C IPD (uA) 120 100 Max. 85°C 80 Typical 60 40 20 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 4.5V 5V 5.5V VDD (V) FIGURE 20-23: LVD IPD vs. VDD OVER TEMPERATURE 80 70 Typical: Statistical Mean @25°C Maximum: Mean + 3σ Max. 125°C 60 IPD (uA) 50 Max. 85°C 40 30 Typical 20 10 0 2.0V 2.5V 3.
PIC16F913/914/916/917/946 FIGURE 20-24: T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz) 30 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) Max. 125°C IPD (uA) 20 15 10 5 2 2.5 3 3.5 4 4.5 5 5.5 Typ 25×C 2.022 2.247 2.472 2.453 2.433 2.711 2.989 3.112 Max 85×C 4.98 5.23 5.49 5.79 6.08 6.54 7.00 7.34 Max 125×C 17.54 19.02 20.29 21.50 Max. 85°C 22.45 23.30 24.00 Typ. 25°C 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-25: VOL vs.
PIC16F913/914/916/917/946 FIGURE 20-26: VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V) 0.45 Typical: Statistical Mean @25°C Typical: Statistical Maximum: Mean + 3σ Mean Maximum: Means + 3 0.40 Max. 125°C 0.35 Max. 85°C VOL (V) 0.30 0.25 Typ. 25°C 0.20 0.15 Min. -40°C 0.10 0.05 0.00 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 IOL (mA) FIGURE 20-27: VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V) 3.5 3.0 Max. -40°C Typ. 25°C 2.5 Min. 125°C VOH (V) 2.0 1.5 1.
PIC16F913/914/916/917/946 FIGURE 20-28: VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V) ( , ) 5.5 5.0 Max. -40°C Typ. 25°C VOH (V) 4.5 Min. 125°C 4.0 3.5 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 IOH (mA) FIGURE 20-29: TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (TTL Input, -40×C TO 125×C) 1.7 1.
PIC16F913/914/916/917/946 FIGURE 20-30: SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE (ST Input, -40×C TO 125×C) 4.0 VIH Max. 125°C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.5 VIH Min. -40°C VIN (V) 3.0 2.5 2.0 VIL Max. -40°C 1.5 VIL Min. 125°C 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-31: 4 5.
PIC16F913/914/916/917/946 FIGURE 20-32: Vdd COMPARATOR RESPONSE TIME (FALLING EDGE) -40×C 25×C 85×C 125×C 2 279 327 547 557 600 2.5 226 267 425 440 4 172 204 304 319 5.5 119 142 182 Response Time (nS) 500 400 300 Max. (125°C) Max. (85°C) 200 Note: 100 VCM = VDD - 1.5V)/2 V+ input = VCM V- input = Transition from VCM - 100MV to VCM + 20MV Typ. (25°C) Min. (-40°C) 0 2.0 2.5 4.0 5.5 VDD (Volts) LFINTOSC FREQUENCY vs.
PIC16F913/914/916/917/946 FIGURE 20-34: ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE 8 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 125°C Time (μs) 6 85°C 25°C 4 -40°C 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-35: TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE 16 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case) + 3σ 14 85°C 12 25°C Time (μs) 10 -40°C 8 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F913/914/916/917/946 FIGURE 20-36: MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 25 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case) + 3σ Time (μs) 20 15 85°C 25°C 10 -40°C 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-37: MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE -40C to +85C 10 9 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 8 Time (μs) 7 85°C 6 25°C 5 -40°C 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.
PIC16F913/914/916/917/946 FIGURE 20-38: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-39: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS41250F-page 302 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 FIGURE 20-40: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 20-41: TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C) 5 4 Change from Calibration (%) 3 2 1 0 -1 -2 -3 -4 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 NOTES: DS41250F-page 304 © 2007 Microchip Technology Inc.
PIC16F913/914/916/917/946 21.0 PACKAGING INFORMATION 21.1 Package Marking Information 28-Lead SPDIP Example PIC16F913 -I/SP e3 0710017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN Example 28-Lead QFN 16F916 -I/ML e3 0710017 XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC16F913/914/916/917/946 Package Marking Information (Continued) 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 64-Lead TQFP (10x10x1mm) XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS41250F-page 306 Example PIC16F914 -I/ML e3 0710017 Example PIC16F913 -I/SO e3 0710017 Example PIC16F916 -I/SS e3 0710017 Exampl
PIC16F913/914/916/917/946 21.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 28 Pitch e Top to Seating Plane A – – .
PIC16F913/914/916/917/946 40-Lead Plastic Dual In-Line (P) – 600 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 40 Pitch e Top to Seating Plane A – – .250 Molded Package Thickness A2 .125 – .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .
PIC16F913/914/916/917/946 28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN] with 0.55 mm Contact Length Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.
PIC16F913/914/916/917/946 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 44 Pitch e Overall Height A 0.80 0.65 BSC 0.90 1.00 Standoff A1 0.00 0.02 0.05 Contact Thickness A3 0.
PIC16F913/914/916/917/946 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 3 b e h α A2 A h c φ L A1 L1 Units Dimension Limits Number of Pins β MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 2.05 – – Standoff § A1 0.10 – 0.
PIC16F913/914/916/917/946 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 28 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.
PIC16F913/914/916/917/946 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A c φ β L A1 Units Dimension Limits Number of Leads A2 L1 MILLIMETERS MIN N NOM MAX 44 Lead Pitch e Overall Height A – 0.80 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.
PIC16F913/914/916/917/946 64-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 NOTE 2 α A c φ A2 β A1 L L1 Units Dimension Limits Number of Leads MILLIMETERS MIN N NOM MAX 64 Lead Pitch e Overall Height A – 0.50 BSC – Molded Package Thickness A2 0.95 1.00 1.05 Standoff A1 0.
PIC16F913/914/916/917/946 APPENDIX A: DATA SHEET REVISION HISTORY Revision A This is a new data sheet. Revision B Updated Peripheral Features. Page 2, Table: Corrected I/O numbers. Figure 8-3: Revised Comparator I/O operating modes. Register 9-1, Table: Corrected max. number of pixels. Revision C Correction to Pin Description Table. Correction to IPD base and T1OSC. Revision D Revised references 31.25 kHz to 31 kHz. Revised Standby Current to 100 nA. Revised 9.
PIC16F913/914/916/917/946 APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
PIC16F917/916/914/913 INDEX A Associated Registers Receive .................................................... 140 Transmit ................................................... 139 Reception ......................................................... 140 Transmission .................................................... 139 A/D Specifications.................................................... 272, 273 Absolute Maximum Ratings ..............................................
PIC16F917/916/914/913 RG Pins....................................................................... 85 SSP (I2C Mode) ........................................................ 202 SSP (SPI Mode)........................................................ 193 Timer1 ....................................................................... 102 Timer2 ....................................................................... 107 TMR0/WDT Prescaler .................................................
PIC16F917/916/914/913 Effects of Reset PWM mode ............................................................... 218 Electrical Specifications .................................................... 255 Errata .................................................................................. 13 F Fail-Safe Clock Monitor....................................................... 97 Fail-Safe Condition Clearing ....................................... 97 Fail-Safe Detection ...........................................
PIC16F917/916/914/913 MPLAB Integrated Development Environment Software .. 251 MPLAB PM3 Device Programmer..................................... 253 MPLAB REAL ICE In-Circuit Emulator System................. 253 MPLINK Object Linker/MPLIB Object Librarian ................ 252 O OPCODE Field Descriptions ............................................. 241 OPTION Register ................................................................ 33 OPTION_REG Register ....................................................
PIC16F917/916/914/913 RF0 ............................................................................. 82 RF1 ............................................................................. 82 RF2 ............................................................................. 82 RF3 ............................................................................. 82 RF4 ............................................................................. 82 RF5 .............................................................
PIC16F917/916/914/913 Serial Data Out (SDO pin) ........................................ 193 Slave Select .............................................................. 193 Slave Select Synchronization ................................... 199 Sleep Operation ........................................................ 201 SPI Clock .................................................................. 198 Typical Connection ...................................................
PIC16F917/916/914/913 Registers..................................................................... 62 TRISC Register ................................................................... 62 TRISD Registers..................................................................... 71 TRISD Register ................................................................... 71 TRISE Registers..................................................................... 76 TRISE Register .............................................
PIC16F917/916/914/913 NOTES: DS41250F-page 324 © 2007 Microchip Technology Inc.
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PIC16F917/916/914/913 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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