Datasheet

© 2007 Microchip Technology Inc. DS41250F-page 231
PIC16F913/914/916/917/946
16.3.1 RB0/INT/SEG0 INTERRUPT
External interrupt on RB0/INT/SEG0 pin is edge-trig-
gered; either rising if the INTEDG bit of the OPTION
register is set, or falling, if the INTEDG bit is clear.
When a valid edge appears on the RB0/INT/SEG0 pin,
the INTF bit of the INTCON register is set. This inter-
rupt can be disabled by clearing the INTE control bit of
the INTCON register. The INTF bit must be cleared in
software in the Interrupt Service Routine before
re-enabling this interrupt. The RB0/INT/SEG0 interrupt
can wake-up the processor from Sleep if the INTE bit
was set prior to going into Sleep. The status of the GIE
bit decides whether or not the processor branches to
the interrupt vector following wake-up (0004h). See
Section 16.5 “Power-Down Mode (Sleep)” for details
on Sleep and Figure 16-10 for timing of wake-up from
Sleep through RB0/INT/SEG0 interrupt.
16.3.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF bit of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
16.3.3 PORTB INTERRUPT
An input change on PORTB change sets the RBIF bit
of the INTCON register. The interrupt can be
enabled/disabled by setting/clearing the RBIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOCB register.
FIGURE 16-7: INTERRUPT LOGIC
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
TMR1IF
TMR1IE
C1IF
C1IE
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)
Interrupt to CPU
PEIF
EEIE
EEIF
ADIF
ADIE
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
CCP2IF
CCP2IE
OSFIF
OSFIE
C2IF
C2IE
CCP1IF
CCP1IE
*
SSPIE
SSPIF
RCIF
RCIE
TXIF
TXIE
LCDIF
LCDIE
LVDIF
LVDIE
TMR2IF
TMR2IE
* Only available on the PIC16F914/917.