Datasheet

PIC16F88X
DS80000302H-page 8  2007-2013 Microchip Technology Inc.
6. Module: MSSP (I
2
C™ Master Mode)
When the MSSP is I
2
C™ Master mode with a
slave device stretching the clock, the clock
generation does not function as described in the
data sheet.
When a slave device is performing clock stretching
by pulling the SCL line low, the master device
should continuously sample the SCL line to deter-
mine when all slaves have released SCL. When
SCL is released, the master device should wait
one BRG period to ensure a constant SCL high
time.
The current implementation does not ensure
accurate SCL high time. During clock stretch, the
MSSP device will erroneously continue running
the BRG counter. At the end of the clock stretch,
the BRG counter continues to count down for the
remainder of the BRG period, and then the MSSP
device will immediately resume transmitting the
data.
Figure 1 illustrates an expected I
2
C transmission
in which the SCL line is completely controlled by
the master device and the slave device does not
attempt to stretch the clock period.
Figure 2 illustrates the expected operation of an
I
2
C transmission in which the slave device has
stretched the clock period by holding the SCL line
low. The high time of the SCL pulse is constant,
regardless of the duration of the clock stretch.
Figure 3 and Figure 4 illustrate an actual I
2
C
transmission in which the slave has stretched the
clock period by holding the SCL line low. Note that
the high time of the SCL signal has shortened from
the expected time.
FIGURE 1: ACTUAL (CORRECT) OPERATION WITHOUT CLOCK STRETCHING
FIGURE 2: EXPECTED OPERATION WITH CLOCK STRETCHING
BRG Period BRG Period BRG Period
BRG Period BRG Period BRG Period
SDA
SCL
Master
Slave
BRG Period
BRG Period
BRG Period
BRG Period
SDA
SCL
Master
Slave