Datasheet

 2007-2013 Microchip Technology Inc. DS80000302H-page 7
PIC16F88X
5. Module: MSSP (I
2
C™ Slave Mode)
When the master device wants to terminate
receiving any more data from the slave device, it
will do so by sending a NACK in response to the
last data byte received from the slave. When the
slave receives the NACK, the R/W bit of the
SSPSTAT register remains set improperly.
Work around
Use the CKP bit of the SSPCON register to
determine when the master has responded with a
NACK. The CKP bit will be clear when the
response is an ACK
, and set when the response is
a NACK. The CKP bit is automatically cleared to
stretch the clock when the master responds to
received data with an ACK
. This gives the slave
time to load the SSPBUF register before setting
the CKP bit to release the clock stretching. When
the master responds to received data with a
NACK, the CKP bit properly remains set and there
is no clock stretching.
Affected Silicon Revisions
PIC16F882
PIC16F883/PIC16F884
PIC16F886/PIC16F887
A0
X
A0
X
A2
X