Datasheet

PIC16F88X
DS80000302H-page 12  2007-2013 Microchip Technology Inc.
9. Module: LP/Timer1 Oscillator Operation
Below 25°C
1-2% of devices experience reduced drive as
temperatures approach -40°C. This will result in a
loss of Timer1 counts or stopped Timer1
oscillation.
This can also prevent Timer1 oscillator start-up
under cold conditions.
Work around
Use of low-power crystals properly matched to the
device will reduce the likelihood of failure. A 1 m
resister between OSC2 and VDD will further
improve the drive strength of the circuit.
Affected Silicon Revisions
PIC16F882
PIC16F883/PIC16F884
PIC16F886/PIC16F887
10. Module: Timer0 and WDT Prescaler
Assignment Spurious Reset
A spurious Reset may occur if the Timer0/
Watchdog Timer (WDT) prescaler is assigned from
the WDT to Timer0 and then back to the WDT.
Summary
The issue only arises when all of the below condi-
tions are met:
• Timer0 external clock input (T0CKI) is
enabled.
• The Prescaler is assigned to the WDT, then
to the Timer0 and back to the WDT.
• During the assignments, the T0CKI pin is
high when bit T0SE is set, or low when T0SE
is clear.
• The 1:1 Prescaler option is chosen.
Description
On a POR, the Timer0/WDT prescaler is assigned
to the WDT.
If the prescaler is reassigned to Timer0 and Timer0
external clock input (T0CKI) is enabled then the
prescaler would be clocked by a transition on the
T0CKI pin.
On power-up, the T0CKI pin is (by default) enabled
for Timer0 in the OPTION register.
If the T0CKI pin is:
• High and Timer0 is configured to transition
on a falling edge (T0SE set), or
• Low and Timer0 is configured to transition
on a rising edge (T0SE clear)
Then, if the prescaler is reassigned to the WDT, a
clock pulse to the prescaler will be generated on
the reassignment.
If the prescaler is configured for the 1:1 option, the
clock pulse will incorrectly cause a WDT Time-out
Reset of the device.
Work around
1. Disable the Timer0 external clock input by
clearing the T0CKI bit in the OPTION
register.
2. Modify the T0SE bit in the OPTION register to
the opposite configuration for the logic level
on the T0CKI pin.
3. Select a prescaler rate other than 1:1 and
issue a CLRWDT instruction before switching
to the final prescaler rate.
Affected Silicon Revisions
PIC16F882
PIC16F883/PIC16F884
PIC16F886/PIC16F887
A0
X
A0
X
A2
X
A0
X
A0
X
A2
X