Datasheet

PIC16F882/883/884/886/887
DS41291F-page 86 © 2009 Microchip Technology Inc.
8.4 Comparator Interrupt Operation
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gate (see Figures 8-2 and 8-3). One latch is updated
with the comparator output level when the CMxCON0
register is read. This latch retains the value until the
next read of the CMxCON0 register or the occurrence
of a Reset. The other latch of the mismatch circuit is
updated on every Q1 system clock. A mismatch
condition will occur when a comparator output change
is clocked through the second latch on the Q1 clock
cycle. At this point the two mismatch latches have
opposite output levels which is detected by the
exclusive-or gate and fed to the interrupt circuitry. The
mismatch condition persists until either the CMxCON0
register is read or the comparator output returns to the
previous state.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the inter-
rupt flag can be reset without the additional step of
reading or writing the CMxCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
Software will need to maintain information about the
status of the comparator output, as read from the
CMxCON0 register, or CM2CON1 register, to determine
the actual change that has occurred.
The CxIF bit of the PIR2 register is the comparator
interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Since it is also possible to write a ‘1’ to
this register, an interrupt can be generated.
The CxIE bit of the PIE2 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CxIF bit of the
PIR2 register will still be set if an interrupt condition
occurs.
FIGURE 8-4: COMPARATOR
INTERRUPT TIMING W/O
CMxCON0 READ
FIGURE 8-5: COMPARATOR
INTERRUPT TIMING WITH
CMxCON0 READ
Note 1: A write operation to the CMxCON0
register will also clear the mismatch
condition because all writes include a read
operation at the beginning of the write
cycle.
2: Comparator interrupts will operate correctly
regardless of the state of CxOE.
Note 1: If a change in the CMxCON0 register
(CxOUT) should occur when a read oper-
ation is being executed (start of the Q2
cycle), then the CxIF of the PIR2 register
interrupt flag may not get set.
2: When either comparator is first enabled,
bias circuitry in the comparator module
may cause an invalid output from the
comparator until the bias circuitry is stable.
Allow about 1 μs for bias settling then clear
the mismatch condition and interrupt flags
before enabling comparator interrupts.
Q1
Q3
C
IN+
CxOUT
Set CxIF (level)
CxIF
TRT
reset by software
Q1
Q3
CxIN+
CxOUT
Set CxIF (level)
CxIF
TRT
reset by software
cleared by CMxCON0 read