Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 20 MHz I/O number 24

 2007-2013 Microchip Technology Inc. DS80000302H-page 1

PIC16F88X

The PIC16F88X family devices that you have received

conform functionally to the current Device Data Sheet

(DS41291G), except for the anomalies described in

this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Tab le 1. The silicon issues are summarized in

Table 2, Table 3 and Table 4.

The errata described in this document will be addressed

in future revisions of the PIC16F88X silicon.

Data Sheet clarifications and corrections start on page

14, following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers, and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level

using MPLAB IDE in conjunction with a hardware

debugger:

1. Using the appropriate interface, connect the

device to the hardware debugger.

2. Open an MPLAB IDE project.

3. Configure the MPLAB IDE project for the

appropriate device and hardware debugger.

4. Based on the version of MPLAB IDE you are

using, do one of the following:

a) For MPLAB IDE 8, select Programmer >

Reconnect.

b) For MPLAB X IDE, select Window >

Dashboard and click the Refresh Debug

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2, Table 3 and Table 4 apply to the

current silicon revision (A0 or A2, as

applicable).

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A0 A2

PIC16F882 2000h 00h

PIC16F883 2020h 00h

PIC16F884 2040h 00h

PIC16F886 2060h

02h

PIC16F887 2080h 02h

Note 1: The device and revision data is stored in the Device ID located at 2006h in program memory.

2: Refer to the “PIC16F88X Memory Programming Specification” (DS41287) for detailed information.

PIC16F88X Family

Silicon Errata and Data Sheet Clarification

Summary of content (18 pages)

PAGE 1
PIC16F88X PIC16F88X Family Silicon Errata and Data Sheet Clarification The PIC16F88X family devices that you have received conform functionally to the current Device Data Sheet (DS41291G), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2, Table 3 and Table 4.
PAGE 2
PIC16F88X TABLE 2: SILICON ISSUE SUMMARY (PIC16F882) Module Feature Item Number Issue Summary Affected Revisions(1) A0 LVP Programming 1. Programming disruption. X MSSP SPI Master 2. SPI using Timer2/2. X ADC VP6 Reference 3. Disruption of the HFINTOSC. X MSSP SPI Master 4. Write collision on loading. X MSSP 2 I C™ Slave 5. R/W bit on ACK. X MSSP I2 6. Clock-stretching handling. X MSSP SPI Slave 7. Multi-byte transmission. X Timer1 Ext. Crystal 8.
PAGE 3
PIC16F88X TABLE 3: SILICON ISSUE SUMMARY (PIC16F883/PIC16F884) Module Feature Item Number Affected Revisions(1) Issue Summary A0 LVP Programming 1. Programming disruption. X MSSP SPI Master 2. SPI using Timer2/2. X ADC VP6 Reference 3. Disruption of the HFINTOSC. X MSSP SPI Master 4. Write collision on loading. X MSSP I2C™ Slave 5. R/W bit on ACK. X MSSP I2 6. Clock-stretching handling. X MSSP SPI Slave 7. Multi-byte transmission. X Timer1 Ext. Crystal 8.
PAGE 4
PIC16F88X TABLE 4: SILICON ISSUE SUMMARY (PIC16F886/PIC16F887) Module Feature Item Number Issue Summary Affected Revisions(1) A2 LVP Programming 1. Programming disruption. X MSSP SPI Master 2. SPI using Timer2/2. X ADC VP6 Reference 3. Disruption of the HFINTOSC. X MSSP SPI Master 4. Write collision on loading. X MSSP I C™ Slave 5. R/W bit on ACK. X MSSP I2 6. Clock-stretching handling. X MSSP SPI Slave 7. Multi-byte transmission. X Timer1 Ext. Crystal 8.
PAGE 5
PIC16F88X Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A0 or A2, as applicable). 2. Module: MSSP (SPI Mode) When the SPI is using Timer2/2 as the clock source, a shorter than expected SCK pulse may occur on the first bit of the transmitted/received data (Figure 1). FIGURE 1: 1.
PAGE 6
PIC16F88X 3. Module: Analog-To-Digital Converter (ADC) Module Selecting the VP6 reference as the analog input source (CHS<3:0> = 1111) for the ADC conversion after sampling another analog channel with input voltages approximately greater than 3.6V can temporarily disturb the HFINTOSC oscillator. Note: This only occurs when selecting the VP6 reference ADC channel using the CHS<3:0> bits in the ADCON0 register and NOT during the start of an actual ADC conversion using the GO/DONE bit in the ADCON0 register.
PAGE 7
PIC16F88X 5. Module: MSSP (I2C™ Slave Mode) When the master device wants to terminate receiving any more data from the slave device, it will do so by sending a NACK in response to the last data byte received from the slave. When the slave receives the NACK, the R/W bit of the SSPSTAT register remains set improperly. Work around Use the CKP bit of the SSPCON register to determine when the master has responded with a NACK.
PAGE 8
PIC16F88X 6. Module: MSSP (I2C™ Master Mode) When the MSSP is I2C™ Master mode with a slave device stretching the clock, the clock generation does not function as described in the data sheet. When a slave device is performing clock stretching by pulling the SCL line low, the master device should continuously sample the SCL line to determine when all slaves have released SCL. When SCL is released, the master device should wait one BRG period to ensure a constant SCL high time.
PAGE 9
PIC16F88X FIGURE 3: ACTUAL (INCORRECT) OPERATION WITH CLOCK STRETCHING – EXAMPLE 1 SDA SCL Master Slave BRG Period FIGURE 4: BRG Period BRG Period BRG Period BRG Period BRG Period ACTUAL (INCORRECT) OPERATION WITH CLOCK STRETCHING – EXAMPLE 2 SDA SCL Master Slave BRG Period BRG Period BRG Period BRG Period BRG Period BRG Period Work around Set the communication speed to match the slowest device on the bus. This ensures that no slave device will perform clock stretching.
PAGE 10
PIC16F88X 7. Module: MSSP When all of the following conditions are met: 1. 2. 3. 4. The module is configured as a SPI slave CKP = 1 CKE = 1 Multiple bytes are sent to the Slave with the SS line remaining low between bytes The SSPIF flag will only be set on reception of the first byte and the following bytes will not be correctly received.
PAGE 11
PIC16F88X 8. Module: Asynchronous Timer1 This Errata supersedes Errata DS80233 and DS80329. When TImer1 is started or updated, the timer needs to see a falling edge from the external clock source before a rising edge can increment the counter. If writes to TMR1H and TMR1L are not completed while the external clock pulse is still high, Timer1 will not count the first clock pulse after the update.
PAGE 12
PIC16F88X 9. Module: LP/Timer1 Oscillator Operation Below 25°C 1-2% of devices experience reduced drive as temperatures approach -40°C. This will result in a loss of Timer1 counts or stopped Timer1 oscillation. This can also prevent Timer1 oscillator start-up under cold conditions. Work around Use of low-power crystals properly matched to the device will reduce the likelihood of failure. A 1 m resister between OSC2 and VDD will further improve the drive strength of the circuit.
PAGE 13
PIC16F88X 11. Module: MSSP (SPI Master Mode) When the MSSP module is configured as a SPI master with CKP set, (SPI clock idles high) disabling the module by clearing the SSPEN bit will cause the clock line to be driven low for 2 TOSC before the setting of the RC3 output in the PORTC register takes effect. Similarly on enabling the module. There is a 1 TOSC period where the clock line will be driven low before the CKP bit takes effect and the line is driven high.
PAGE 14
PIC16F88X Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41291G): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: ADC (Block Diagram) Figure 9-1: ADC Block Diagram changes references from AVSS to VSS and AVDD to VDD. 2. Module: ADC Acquisition Time Example calculation correction.
PAGE 15
PIC16F88X APPENDIX A: DOCUMENT REVISION HISTORY REV. A DOCUMENT (2/2007) First revision of this document. Added Module 1: Low-Voltage In-Circuit Serial Programming™ (PIC16F884/883 Silicon Rev. A0); Added Module 2: MSSP (SPI Mode). Clarifications/Corrections to the Data Sheet – Added Module 1: Product Identification System. REV. B DOCUMENT (5/2007) Clarifications/Corrections to the Data Sheet – Added Module 2: Electrical Specification - Supply Current. REV.
PAGE 16
PIC16F88X NOTES: DS80000302H-page 16  2007-2013 Microchip Technology Inc.
PAGE 17
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 18
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.